| fs.py (12564:2778478ca882) | fs.py (12598:b80b2d9a251b) |
|---|---|
| 1# Copyright (c) 2010-2013, 2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 138 unchanged lines hidden (view full) --- 147 # For now, assign all the CPUs to the same clock domain 148 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 149 for i in xrange(np)] 150 151 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 152 test_sys.kvm_vm = KvmVM() 153 154 if options.ruby: | 1# Copyright (c) 2010-2013, 2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 138 unchanged lines hidden (view full) --- 147 # For now, assign all the CPUs to the same clock domain 148 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 149 for i in xrange(np)] 150 151 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 152 test_sys.kvm_vm = KvmVM() 153 154 if options.ruby: |
| 155 bootmem = getattr(test_sys, 'bootmem', None) |
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| 155 Ruby.create_system(options, True, test_sys, test_sys.iobus, | 156 Ruby.create_system(options, True, test_sys, test_sys.iobus, |
| 156 test_sys._dma_ports) | 157 test_sys._dma_ports, bootmem) |
| 157 158 # Create a seperate clock domain for Ruby 159 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 160 voltage_domain = test_sys.voltage_domain) 161 162 # Connect the ruby io port to the PIO bus, 163 # assuming that there is just one such port. 164 test_sys.iobus.master = test_sys.ruby._io_port.slave --- 234 unchanged lines hidden --- | 158 159 # Create a seperate clock domain for Ruby 160 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 161 voltage_domain = test_sys.voltage_domain) 162 163 # Connect the ruby io port to the PIO bus, 164 # assuming that there is just one such port. 165 test_sys.iobus.master = test_sys.ruby._io_port.slave --- 234 unchanged lines hidden --- |