fs.py (12395:322bb93e5f06) fs.py (12475:c6a23d6370de)
1# Copyright (c) 2010-2013, 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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43
44import optparse
45import sys
46
47import m5
48from m5.defines import buildEnv
49from m5.objects import *
50from m5.util import addToPath, fatal, warn
1# Copyright (c) 2010-2013, 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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43
44import optparse
45import sys
46
47import m5
48from m5.defines import buildEnv
49from m5.objects import *
50from m5.util import addToPath, fatal, warn
51from m5.util.fdthelper import *
51
52addToPath('../')
53
54from ruby import Ruby
55
56from common.FSConfig import *
57from common.SysPaths import *
58from common.Benchmarks import *

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94 elif buildEnv['TARGET_ISA'] == "x86":
95 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
96 options.ruby, cmdline=cmdline)
97 elif buildEnv['TARGET_ISA'] == "arm":
98 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
99 options.num_cpus, bm[0], options.dtb_filename,
100 bare_metal=options.bare_metal,
101 cmdline=cmdline,
52
53addToPath('../')
54
55from ruby import Ruby
56
57from common.FSConfig import *
58from common.SysPaths import *
59from common.Benchmarks import *

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95 elif buildEnv['TARGET_ISA'] == "x86":
96 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
97 options.ruby, cmdline=cmdline)
98 elif buildEnv['TARGET_ISA'] == "arm":
99 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
100 options.num_cpus, bm[0], options.dtb_filename,
101 bare_metal=options.bare_metal,
102 cmdline=cmdline,
102 external_memory=options.external_memory_system,
103 ignore_dtb=options.generate_dtb,
104 external_memory=
105 options.external_memory_system,
103 ruby=options.ruby,
104 security=options.enable_security_extensions)
105 if options.enable_context_switch_stats_dump:
106 test_sys.enable_context_switch_stats_dump = True
107 else:
108 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
109
110 # Set the cache line size for the entire system

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243 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
244 elif buildEnv['TARGET_ISA'] == 'sparc':
245 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
246 elif buildEnv['TARGET_ISA'] == 'x86':
247 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
248 cmdline=cmdline)
249 elif buildEnv['TARGET_ISA'] == 'arm':
250 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
106 ruby=options.ruby,
107 security=options.enable_security_extensions)
108 if options.enable_context_switch_stats_dump:
109 test_sys.enable_context_switch_stats_dump = True
110 else:
111 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
112
113 # Set the cache line size for the entire system

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246 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
247 elif buildEnv['TARGET_ISA'] == 'sparc':
248 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
249 elif buildEnv['TARGET_ISA'] == 'x86':
250 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
251 cmdline=cmdline)
252 elif buildEnv['TARGET_ISA'] == 'arm':
253 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
251 bm[1], options.dtb_filename, cmdline=cmdline)
254 bm[1], options.dtb_filename, cmdline=cmdline,
255 ignore_dtb=options.generate_dtb)
252
253 # Create a top-level voltage domain
254 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
255
256 # Create a source clock for the system and set the clock period
257 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
258 voltage_domain = drive_sys.voltage_domain)
259

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357 sys.exit(1)
358
359if options.timesync:
360 root.time_sync_enable = True
361
362if options.frame_capture:
363 VncServer.frame_capture = True
364
256
257 # Create a top-level voltage domain
258 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
259
260 # Create a source clock for the system and set the clock period
261 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
262 voltage_domain = drive_sys.voltage_domain)
263

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361 sys.exit(1)
362
363if options.timesync:
364 root.time_sync_enable = True
365
366if options.frame_capture:
367 VncServer.frame_capture = True
368
369if buildEnv['TARGET_ISA'] == "arm" and options.generate_dtb:
370 # Sanity checks
371 if options.dtb_filename:
372 fatal("--generate-dtb and --dtb-filename cannot be specified at the"\
373 "same time.")
374
375 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
376 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
377 "platforms, unless custom hardware models have been equipped "\
378 "with generation functionality.")
379
380 # Generate a Device Tree
381 def create_dtb_for_system(system, filename):
382 state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
383 rootNode = system.generateDeviceTree(state)
384
385 fdt = Fdt()
386 fdt.add_rootnode(rootNode)
387 dtb_filename = os.path.join(m5.options.outdir, filename)
388 return fdt.writeDtbFile(dtb_filename)
389
390 for sysname in ('system', 'testsys', 'drivesys'):
391 if hasattr(root, sysname):
392 sys = getattr(root, sysname)
393 sys.dtb_filename = create_dtb_for_system(sys, '%s.dtb' % sysname)
394
395elif buildEnv['TARGET_ISA'] != "arm" and options.generate_dtb:
396 fatal("Can only generate dtb files for ARM systems.")
397
365Simulation.setWorkCountOptions(test_sys, options)
366Simulation.run(options, root, test_sys, FutureClass)
398Simulation.setWorkCountOptions(test_sys, options)
399Simulation.run(options, root, test_sys, FutureClass)