| fs.py (11291:9d2364203316) | fs.py (11598:e0ddee91eb13) |
|---|---|
| 1# Copyright (c) 2010-2013 ARM Limited | 1# Copyright (c) 2010-2013, 2016 ARM Limited |
| 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 84 unchanged lines hidden (view full) --- 94 elif buildEnv['TARGET_ISA'] == "x86": 95 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 96 options.ruby, cmdline=cmdline) 97 elif buildEnv['TARGET_ISA'] == "arm": 98 test_sys = makeArmSystem(test_mem_mode, options.machine_type, 99 options.num_cpus, bm[0], options.dtb_filename, 100 bare_metal=options.bare_metal, 101 cmdline=cmdline, | 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 84 unchanged lines hidden (view full) --- 94 elif buildEnv['TARGET_ISA'] == "x86": 95 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 96 options.ruby, cmdline=cmdline) 97 elif buildEnv['TARGET_ISA'] == "arm": 98 test_sys = makeArmSystem(test_mem_mode, options.machine_type, 99 options.num_cpus, bm[0], options.dtb_filename, 100 bare_metal=options.bare_metal, 101 cmdline=cmdline, |
| 102 external_memory=options.external_memory_system) | 102 external_memory=options.external_memory_system, 103 ruby=options.ruby) |
| 103 if options.enable_context_switch_stats_dump: 104 test_sys.enable_context_switch_stats_dump = True 105 else: 106 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 107 108 # Set the cache line size for the entire system 109 test_sys.cache_line_size = options.cacheline_size 110 --- 56 unchanged lines hidden (view full) --- 167 # 168 cpu.clk_domain = test_sys.cpu_clk_domain 169 cpu.createThreads() 170 cpu.createInterruptController() 171 172 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 173 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 174 | 104 if options.enable_context_switch_stats_dump: 105 test_sys.enable_context_switch_stats_dump = True 106 else: 107 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 108 109 # Set the cache line size for the entire system 110 test_sys.cache_line_size = options.cacheline_size 111 --- 56 unchanged lines hidden (view full) --- 168 # 169 cpu.clk_domain = test_sys.cpu_clk_domain 170 cpu.createThreads() 171 cpu.createInterruptController() 172 173 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 174 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 175 |
| 175 if buildEnv['TARGET_ISA'] == "x86": | 176 if buildEnv['TARGET_ISA'] in ("x86", "arm"): |
| 176 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 177 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 178 | 177 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 178 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 179 |
| 180 if buildEnv['TARGET_ISA'] in "x86": |
|
| 179 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 180 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 181 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 182 183 else: 184 if options.caches or options.l2cache: 185 # By default the IOCache runs at the system clock 186 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) --- 182 unchanged lines hidden --- | 181 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 182 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 183 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 184 185 else: 186 if options.caches or options.l2cache: 187 # By default the IOCache runs at the system clock 188 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) --- 182 unchanged lines hidden --- |