| fs.py (10780:46070443051e) | fs.py (11150:a8a64cca231b) |
|---|---|
| 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 162 unchanged lines hidden (view full) --- 171 172 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 173 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 174 175 if buildEnv['TARGET_ISA'] == "x86": 176 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 177 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 178 | 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 162 unchanged lines hidden (view full) --- 171 172 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 173 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 174 175 if buildEnv['TARGET_ISA'] == "x86": 176 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 177 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 178 |
| 179 cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master 180 cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave 181 cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master | 179 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 180 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 181 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master |
| 182 183 else: 184 if options.caches or options.l2cache: 185 # By default the IOCache runs at the system clock 186 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 187 test_sys.iocache.cpu_side = test_sys.iobus.master 188 test_sys.iocache.mem_side = test_sys.membus.slave 189 elif not options.external_memory_system: --- 155 unchanged lines hidden --- | 182 183 else: 184 if options.caches or options.l2cache: 185 # By default the IOCache runs at the system clock 186 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 187 test_sys.iocache.cpu_side = test_sys.iobus.master 188 test_sys.iocache.mem_side = test_sys.membus.slave 189 elif not options.external_memory_system: --- 155 unchanged lines hidden --- |