fs.py (10747:3fe41011333d) fs.py (10780:46070443051e)
1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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93 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
94 elif buildEnv['TARGET_ISA'] == "x86":
95 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
96 options.ruby, cmdline=cmdline)
97 elif buildEnv['TARGET_ISA'] == "arm":
98 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
99 options.num_cpus, bm[0], options.dtb_filename,
100 bare_metal=options.bare_metal,
1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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93 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
94 elif buildEnv['TARGET_ISA'] == "x86":
95 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
96 options.ruby, cmdline=cmdline)
97 elif buildEnv['TARGET_ISA'] == "arm":
98 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
99 options.num_cpus, bm[0], options.dtb_filename,
100 bare_metal=options.bare_metal,
101 cmdline=cmdline)
101 cmdline=cmdline,
102 external_memory=options.external_memory_system)
102 if options.enable_context_switch_stats_dump:
103 test_sys.enable_context_switch_stats_dump = True
104 else:
105 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
106
107 # Set the cache line size for the entire system
108 test_sys.cache_line_size = options.cacheline_size
109

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180 cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
181
182 else:
183 if options.caches or options.l2cache:
184 # By default the IOCache runs at the system clock
185 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
186 test_sys.iocache.cpu_side = test_sys.iobus.master
187 test_sys.iocache.mem_side = test_sys.membus.slave
103 if options.enable_context_switch_stats_dump:
104 test_sys.enable_context_switch_stats_dump = True
105 else:
106 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
107
108 # Set the cache line size for the entire system
109 test_sys.cache_line_size = options.cacheline_size
110

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181 cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
182
183 else:
184 if options.caches or options.l2cache:
185 # By default the IOCache runs at the system clock
186 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
187 test_sys.iocache.cpu_side = test_sys.iobus.master
188 test_sys.iocache.mem_side = test_sys.membus.slave
188 else:
189 elif not options.external_memory_system:
189 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
190 test_sys.iobridge.slave = test_sys.iobus.master
191 test_sys.iobridge.master = test_sys.membus.slave
192
193 # Sanity check
194 if options.fastmem:
195 if TestCPUClass != AtomicSimpleCPU:
196 fatal("Fastmem can only be used with atomic CPU!")

--- 147 unchanged lines hidden --- 		190 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
191 test_sys.iobridge.slave = test_sys.iobus.master
192 test_sys.iobridge.master = test_sys.membus.slave
193
194 # Sanity check
195 if options.fastmem:
196 if TestCPUClass != AtomicSimpleCPU:
197 fatal("Fastmem can only be used with atomic CPU!")

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