| fs.py (10608:427f988fe6e5) | fs.py (10635:ab05a080d7c5) |
|---|---|
| 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 222 unchanged lines hidden (view full) --- 231 elif buildEnv['TARGET_ISA'] == 'mips': 232 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 233 elif buildEnv['TARGET_ISA'] == 'sparc': 234 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 235 elif buildEnv['TARGET_ISA'] == 'x86': 236 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 237 cmdline=cmdline) 238 elif buildEnv['TARGET_ISA'] == 'arm': | 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 222 unchanged lines hidden (view full) --- 231 elif buildEnv['TARGET_ISA'] == 'mips': 232 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 233 elif buildEnv['TARGET_ISA'] == 'sparc': 234 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 235 elif buildEnv['TARGET_ISA'] == 'x86': 236 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 237 cmdline=cmdline) 238 elif buildEnv['TARGET_ISA'] == 'arm': |
| 239 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1], 240 cmdline=cmdline) | 239 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 240 bm[1], options.dtb_filename, cmdline=cmdline) |
| 241 242 # Create a top-level voltage domain 243 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 244 245 # Create a source clock for the system and set the clock period 246 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 247 voltage_domain = drive_sys.voltage_domain) 248 --- 92 unchanged lines hidden --- | 241 242 # Create a top-level voltage domain 243 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 244 245 # Create a source clock for the system and set the clock period 246 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 247 voltage_domain = drive_sys.voltage_domain) 248 --- 92 unchanged lines hidden --- |