| fs.py (10524:fff17530cef6) | fs.py (10547:b61dc895269a) |
|---|---|
| 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 128 unchanged lines hidden (view full) --- 137 138 Ruby.create_system(options, True, test_sys, test_sys.iobus, 139 test_sys._dma_ports) 140 141 # Create a seperate clock domain for Ruby 142 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 143 voltage_domain = test_sys.voltage_domain) 144 | 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 128 unchanged lines hidden (view full) --- 137 138 Ruby.create_system(options, True, test_sys, test_sys.iobus, 139 test_sys._dma_ports) 140 141 # Create a seperate clock domain for Ruby 142 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 143 voltage_domain = test_sys.voltage_domain) 144 |
| 145 # Connect the ruby io port to the PIO bus, 146 # assuming that there is just one such port. 147 test_sys.iobus.master = test_sys.ruby._io_port.slave 148 |
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| 145 for (i, cpu) in enumerate(test_sys.cpu): 146 # 147 # Tie the cpu ports to the correct ruby system ports 148 # 149 cpu.clk_domain = test_sys.cpu_clk_domain 150 cpu.createThreads() 151 cpu.createInterruptController() 152 153 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 154 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 155 156 if buildEnv['TARGET_ISA'] == "x86": 157 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 158 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 159 160 cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master 161 cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave 162 cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master 163 | 149 for (i, cpu) in enumerate(test_sys.cpu): 150 # 151 # Tie the cpu ports to the correct ruby system ports 152 # 153 cpu.clk_domain = test_sys.cpu_clk_domain 154 cpu.createThreads() 155 cpu.createInterruptController() 156 157 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 158 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 159 160 if buildEnv['TARGET_ISA'] == "x86": 161 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 162 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 163 164 cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master 165 cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave 166 cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master 167 |
| 164 # Connect the ruby io port to the PIO bus, 165 # assuming that there is just one such port. 166 test_sys.iobus.master = test_sys.ruby._io_port.slave 167 | |
| 168 else: 169 if options.caches or options.l2cache: 170 # By default the IOCache runs at the system clock 171 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 172 test_sys.iocache.cpu_side = test_sys.iobus.master 173 test_sys.iocache.mem_side = test_sys.membus.slave 174 else: 175 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) --- 139 unchanged lines hidden --- | 168 else: 169 if options.caches or options.l2cache: 170 # By default the IOCache runs at the system clock 171 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 172 test_sys.iocache.cpu_side = test_sys.iobus.master 173 test_sys.iocache.mem_side = test_sys.membus.slave 174 else: 175 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) --- 139 unchanged lines hidden --- |