| fs.py (10519:7a3ad4b09ce4) | fs.py (10524:fff17530cef6) |
|---|---|
| 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 123 unchanged lines hidden (view full) --- 132 if options.ruby: 133 # Check for timing mode because ruby does not support atomic accesses 134 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 135 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 136 sys.exit(1) 137 138 Ruby.create_system(options, True, test_sys, test_sys.iobus, 139 test_sys._dma_ports) | 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 123 unchanged lines hidden (view full) --- 132 if options.ruby: 133 # Check for timing mode because ruby does not support atomic accesses 134 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 135 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 136 sys.exit(1) 137 138 Ruby.create_system(options, True, test_sys, test_sys.iobus, 139 test_sys._dma_ports) |
| 140 test_sys.physmem = [SimpleMemory(range = r, null = True) 141 for r in test_sys.mem_ranges] | |
| 142 143 # Create a seperate clock domain for Ruby 144 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 145 voltage_domain = test_sys.voltage_domain) 146 147 for (i, cpu) in enumerate(test_sys.cpu): 148 # 149 # Tie the cpu ports to the correct ruby system ports --- 167 unchanged lines hidden --- | 140 141 # Create a seperate clock domain for Ruby 142 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 143 voltage_domain = test_sys.voltage_domain) 144 145 for (i, cpu) in enumerate(test_sys.cpu): 146 # 147 # Tie the cpu ports to the correct ruby system ports --- 167 unchanged lines hidden --- |