fs.py (10512:b423e1d0735e) fs.py (10519:7a3ad4b09ce4)
1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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130 test_sys.vm = KvmVM()
131
132 if options.ruby:
133 # Check for timing mode because ruby does not support atomic accesses
134 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
135 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
136 sys.exit(1)
137
1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 121 unchanged lines hidden (view full) ---

130 test_sys.vm = KvmVM()
131
132 if options.ruby:
133 # Check for timing mode because ruby does not support atomic accesses
134 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
135 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
136 sys.exit(1)
137
138 Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
138 Ruby.create_system(options, True, test_sys, test_sys.iobus,
139 test_sys._dma_ports)
140 test_sys.physmem = [SimpleMemory(range = r, null = True)
141 for r in test_sys.mem_ranges]
139
140 # Create a seperate clock domain for Ruby
141 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
142 voltage_domain = test_sys.voltage_domain)
143
144 for (i, cpu) in enumerate(test_sys.cpu):
145 #
146 # Tie the cpu ports to the correct ruby system ports

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155 if buildEnv['TARGET_ISA'] == "x86":
156 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
157 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
158
159 cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
160 cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
161 cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
162
142
143 # Create a seperate clock domain for Ruby
144 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
145 voltage_domain = test_sys.voltage_domain)
146
147 for (i, cpu) in enumerate(test_sys.cpu):
148 #
149 # Tie the cpu ports to the correct ruby system ports

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158 if buildEnv['TARGET_ISA'] == "x86":
159 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
160 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
161
162 cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
163 cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
164 cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
165
163 test_sys.ruby._cpu_ports[i].access_phys_mem = True
166 # Connect the ruby io port to the PIO bus,
167 # assuming that there is just one such port.
168 test_sys.iobus.master = test_sys.ruby._io_port.slave
164
169
165 # Create the appropriate memory controllers
166 # and connect them to the IO bus
167 test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
168 for i in xrange(len(test_sys.mem_ctrls)):
169 test_sys.mem_ctrls[i].port = test_sys.iobus.master
170
171 else:
172 if options.caches or options.l2cache:
173 # By default the IOCache runs at the system clock
174 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
175 test_sys.iocache.cpu_side = test_sys.iobus.master
176 test_sys.iocache.mem_side = test_sys.membus.slave
177 else:
178 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)

--- 139 unchanged lines hidden --- 		170 else:
171 if options.caches or options.l2cache:
172 # By default the IOCache runs at the system clock
173 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
174 test_sys.iocache.cpu_side = test_sys.iobus.master
175 test_sys.iocache.mem_side = test_sys.membus.slave
176 else:
177 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)

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