| fs.py (10119:6f3f839bb496) | fs.py (10120:f5ceb3c3edb6) |
|---|---|
| 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 135 unchanged lines hidden (view full) --- 144 for (i, cpu) in enumerate(test_sys.cpu): 145 # 146 # Tie the cpu ports to the correct ruby system ports 147 # 148 cpu.clk_domain = test_sys.cpu_clk_domain 149 cpu.createThreads() 150 cpu.createInterruptController() 151 | 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 135 unchanged lines hidden (view full) --- 144 for (i, cpu) in enumerate(test_sys.cpu): 145 # 146 # Tie the cpu ports to the correct ruby system ports 147 # 148 cpu.clk_domain = test_sys.cpu_clk_domain 149 cpu.createThreads() 150 cpu.createInterruptController() 151 |
| 152 cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave 153 cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave | 152 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 153 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave |
| 154 155 if buildEnv['TARGET_ISA'] == "x86": | 154 155 if buildEnv['TARGET_ISA'] == "x86": |
| 156 cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave 157 cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave | 156 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 157 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave |
| 158 | 158 |
| 159 cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master 160 cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave 161 cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master | 159 cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master 160 cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave 161 cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master |
| 162 | 162 |
| 163 test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True | 163 test_sys.ruby._cpu_ports[i].access_phys_mem = True |
| 164 165 # Create the appropriate memory controllers 166 # and connect them to the IO bus 167 test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] 168 for i in xrange(len(test_sys.mem_ctrls)): 169 test_sys.mem_ctrls[i].port = test_sys.iobus.master 170 171 else: --- 146 unchanged lines hidden --- | 164 165 # Create the appropriate memory controllers 166 # and connect them to the IO bus 167 test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] 168 for i in xrange(len(test_sys.mem_ctrls)): 169 test_sys.mem_ctrls[i].port = test_sys.iobus.master 170 171 else: --- 146 unchanged lines hidden --- |