| fs.py (10041:fae4550d2103) | fs.py (10056:33db5d81c2cb) |
|---|---|
| 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 177 unchanged lines hidden (view full) --- 186if len(bm) == 2: 187 if buildEnv['TARGET_ISA'] == 'alpha': 188 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 189 elif buildEnv['TARGET_ISA'] == 'mips': 190 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 191 elif buildEnv['TARGET_ISA'] == 'sparc': 192 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 193 elif buildEnv['TARGET_ISA'] == 'x86': | 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 177 unchanged lines hidden (view full) --- 186if len(bm) == 2: 187 if buildEnv['TARGET_ISA'] == 'alpha': 188 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 189 elif buildEnv['TARGET_ISA'] == 'mips': 190 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 191 elif buildEnv['TARGET_ISA'] == 'sparc': 192 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 193 elif buildEnv['TARGET_ISA'] == 'x86': |
| 194 drive_sys = makeX86System(drive_mem_mode, np, bm[1]) | 194 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1]) |
| 195 elif buildEnv['TARGET_ISA'] == 'arm': 196 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 197 198 # Create a top-level voltage domain 199 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 200 201 # Create a source clock for the system and set the clock period 202 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) --- 50 unchanged lines hidden --- | 195 elif buildEnv['TARGET_ISA'] == 'arm': 196 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 197 198 # Create a top-level voltage domain 199 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 200 201 # Create a source clock for the system and set the clock period 202 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) --- 50 unchanged lines hidden --- |