1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40 41import optparse 42import sys 43 44import m5 45from m5.defines import buildEnv 46from m5.objects import * 47from m5.util import addToPath, fatal 48 49addToPath('../common') 50 51from FSConfig import * 52from SysPaths import * 53from Benchmarks import * 54import Simulation 55import CacheConfig 56import MemConfig 57from Caches import * 58import Options 59 60parser = optparse.OptionParser() 61Options.addCommonOptions(parser) 62Options.addFSOptions(parser) 63 64(options, args) = parser.parse_args() 65 66if args: 67 print "Error: script doesn't take any positional arguments" 68 sys.exit(1) 69 70# driver system CPU is always simple... note this is an assignment of 71# a class, not an instance. 72DriveCPUClass = AtomicSimpleCPU 73drive_mem_mode = 'atomic' 74 75# Check if KVM support has been enabled, we might need to do VM 76# configuration if that's the case. 77have_kvm_support = 'BaseKvmCPU' in globals() 78def is_kvm_cpu(cpu_class): 79 return have_kvm_support and cpu_class != None and \ 80 issubclass(cpu_class, BaseKvmCPU) 81 82# system under test can be any CPU 83(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 84 85# Match the memories with the CPUs, the driver system always simple, 86# and based on the options for the test system 87DriveMemClass = SimpleMemory 88TestMemClass = Simulation.setMemClass(options) 89 90if options.benchmark: 91 try: 92 bm = Benchmarks[options.benchmark] 93 except KeyError: 94 print "Error benchmark %s has not been defined." % options.benchmark 95 print "Valid benchmarks are: %s" % DefinedBenchmarks 96 sys.exit(1) 97else: 98 if options.dual: 99 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 100 else: 101 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 102 103np = options.num_cpus 104 105if buildEnv['TARGET_ISA'] == "alpha": 106 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 107elif buildEnv['TARGET_ISA'] == "mips": 108 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 109elif buildEnv['TARGET_ISA'] == "sparc": 110 test_sys = makeSparcSystem(test_mem_mode, bm[0]) 111elif buildEnv['TARGET_ISA'] == "x86": 112 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) 113elif buildEnv['TARGET_ISA'] == "arm": 114 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 115 options.dtb_filename, 116 bare_metal=options.bare_metal) 117 if options.enable_context_switch_stats_dump: 118 test_sys.enable_context_switch_stats_dump = True 119else: 120 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 121 122# Create a top-level voltage domain 123test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 124 125# Create a source clock for the system and set the clock period 126test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 127 voltage_domain = test_sys.voltage_domain) 128 129# Create a CPU voltage domain 130test_sys.cpu_voltage_domain = VoltageDomain() 131 132# Create a source clock for the CPUs and set the clock period 133test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 134 voltage_domain = 135 test_sys.cpu_voltage_domain) 136 137if options.kernel is not None: 138 test_sys.kernel = binary(options.kernel) 139 140if options.script is not None: 141 test_sys.readfile = options.script 142
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149test_sys.init_param = options.init_param 150 151# For now, assign all the CPUs to the same clock domain 152test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 153 for i in xrange(np)] 154 155if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 156 test_sys.vm = KvmVM() 157 158if options.caches or options.l2cache: 159 # By default the IOCache runs at the system clock 160 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 161 test_sys.iocache.cpu_side = test_sys.iobus.master 162 test_sys.iocache.mem_side = test_sys.membus.slave 163else: 164 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 165 test_sys.iobridge.slave = test_sys.iobus.master 166 test_sys.iobridge.master = test_sys.membus.slave 167 168# Sanity check 169if options.fastmem: 170 if TestCPUClass != AtomicSimpleCPU: 171 fatal("Fastmem can only be used with atomic CPU!") 172 if (options.caches or options.l2cache): 173 fatal("You cannot use fastmem in combination with caches!") 174 175for i in xrange(np): 176 if options.fastmem: 177 test_sys.cpu[i].fastmem = True 178 if options.checker: 179 test_sys.cpu[i].addCheckerCpu() 180 test_sys.cpu[i].createThreads() 181 182CacheConfig.config_cache(options, test_sys) 183MemConfig.config_mem(options, test_sys) 184 185if len(bm) == 2: 186 if buildEnv['TARGET_ISA'] == 'alpha': 187 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 188 elif buildEnv['TARGET_ISA'] == 'mips': 189 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 190 elif buildEnv['TARGET_ISA'] == 'sparc': 191 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 192 elif buildEnv['TARGET_ISA'] == 'x86': 193 drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 194 elif buildEnv['TARGET_ISA'] == 'arm': 195 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 196 197 # Create a top-level voltage domain 198 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 199 200 # Create a source clock for the system and set the clock period 201 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock) 202 203 # Create a CPU voltage domain 204 drive_sys.cpu_voltage_domain = VoltageDomain() 205 206 # Create a source clock for the CPUs and set the clock period 207 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 208 voltage_domain = 209 drive_sys.cpu_voltage_domain) 210 211 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 212 cpu_id=0) 213 drive_sys.cpu.createThreads() 214 drive_sys.cpu.createInterruptController() 215 drive_sys.cpu.connectAllPorts(drive_sys.membus) 216 if options.fastmem: 217 drive_sys.cpu.fastmem = True 218 if options.kernel is not None: 219 drive_sys.kernel = binary(options.kernel) 220 221 if is_kvm_cpu(DriveCPUClass): 222 drive_sys.vm = KvmVM() 223 224 drive_sys.iobridge = Bridge(delay='50ns', 225 ranges = drive_sys.mem_ranges) 226 drive_sys.iobridge.slave = drive_sys.iobus.master 227 drive_sys.iobridge.master = drive_sys.membus.slave 228 229 # Create the appropriate memory controllers and connect them to the 230 # memory bus 231 drive_sys.mem_ctrls = [DriveMemClass(range = r) 232 for r in drive_sys.mem_ranges] 233 for i in xrange(len(drive_sys.mem_ctrls)): 234 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 235 236 drive_sys.init_param = options.init_param 237 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 238elif len(bm) == 1: 239 root = Root(full_system=True, system=test_sys) 240else: 241 print "Error I don't know how to create more than 2 systems." 242 sys.exit(1) 243 244if options.timesync: 245 root.time_sync_enable = True 246 247if options.frame_capture: 248 VncServer.frame_capture = True 249 250Simulation.setWorkCountOptions(test_sys, options) 251Simulation.run(options, root, test_sys, FutureClass)
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