1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40 41import optparse 42import sys 43 44import m5 45from m5.defines import buildEnv 46from m5.objects import * 47from m5.util import addToPath, fatal 48 49addToPath('../common') 50 51from FSConfig import * 52from SysPaths import * 53from Benchmarks import * 54import Simulation 55import CacheConfig 56from Caches import * 57import Options 58 59parser = optparse.OptionParser() 60Options.addCommonOptions(parser) 61Options.addFSOptions(parser) 62 63(options, args) = parser.parse_args() 64 65if args: 66 print "Error: script doesn't take any positional arguments" 67 sys.exit(1) 68 69# driver system CPU is always simple... note this is an assignment of 70# a class, not an instance. 71DriveCPUClass = AtomicSimpleCPU 72drive_mem_mode = 'atomic' 73 74# Check if KVM support has been enabled, we might need to do VM 75# configuration if that's the case. 76have_kvm_support = 'BaseKvmCPU' in globals() 77def is_kvm_cpu(cpu_class): 78 return have_kvm_support and cpu_class != None and \ 79 issubclass(cpu_class, BaseKvmCPU) 80 81# system under test can be any CPU 82(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 83 84TestCPUClass.clock = options.cpu_clock 85DriveCPUClass.clock = options.cpu_clock 86 87# Match the memories with the CPUs, the driver system always simple, 88# and based on the options for the test system 89DriveMemClass = SimpleMemory 90TestMemClass = Simulation.setMemClass(options) 91 92if options.benchmark: 93 try: 94 bm = Benchmarks[options.benchmark] 95 except KeyError: 96 print "Error benchmark %s has not been defined." % options.benchmark 97 print "Valid benchmarks are: %s" % DefinedBenchmarks 98 sys.exit(1) 99else: 100 if options.dual: 101 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)] 102 else: 103 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 104 105np = options.num_cpus 106 107if buildEnv['TARGET_ISA'] == "alpha": 108 test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0]) 109elif buildEnv['TARGET_ISA'] == "mips": 110 test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0]) 111elif buildEnv['TARGET_ISA'] == "sparc": 112 test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0]) 113elif buildEnv['TARGET_ISA'] == "x86": 114 test_sys = makeLinuxX86System(test_mem_mode, TestMemClass, 115 options.num_cpus, bm[0]) 116elif buildEnv['TARGET_ISA'] == "arm": 117 test_sys = makeArmSystem(test_mem_mode, options.machine_type, 118 TestMemClass, bm[0], options.dtb_filename, 119 bare_metal=options.bare_metal) 120else: 121 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 122
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125if options.kernel is not None: 126 test_sys.kernel = binary(options.kernel) 127 128if options.script is not None: 129 test_sys.readfile = options.script 130 131test_sys.init_param = options.init_param 132 133test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 134 135if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 136 test_sys.vm = KvmVM() 137 138if options.caches or options.l2cache: 139 # By default the IOCache runs at the system clock 140 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 141 test_sys.iocache.cpu_side = test_sys.iobus.master 142 test_sys.iocache.mem_side = test_sys.membus.slave 143else: 144 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 145 test_sys.iobridge.slave = test_sys.iobus.master 146 test_sys.iobridge.master = test_sys.membus.slave 147 148# Sanity check 149if options.fastmem: 150 if TestCPUClass != AtomicSimpleCPU: 151 fatal("Fastmem can only be used with atomic CPU!") 152 if (options.caches or options.l2cache): 153 fatal("You cannot use fastmem in combination with caches!") 154 155for i in xrange(np): 156 if options.fastmem: 157 test_sys.cpu[i].fastmem = True 158 if options.checker: 159 test_sys.cpu[i].addCheckerCpu() 160 test_sys.cpu[i].createThreads() 161 162CacheConfig.config_cache(options, test_sys) 163 164if len(bm) == 2: 165 if buildEnv['TARGET_ISA'] == 'alpha': 166 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, bm[1]) 167 elif buildEnv['TARGET_ISA'] == 'mips': 168 drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, bm[1]) 169 elif buildEnv['TARGET_ISA'] == 'sparc': 170 drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1]) 171 elif buildEnv['TARGET_ISA'] == 'x86': 172 drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1]) 173 elif buildEnv['TARGET_ISA'] == 'arm': 174 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, 175 DriveMemClass, bm[1]) 176
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179 drive_sys.cpu = DriveCPUClass(cpu_id=0) 180 drive_sys.cpu.createThreads() 181 drive_sys.cpu.createInterruptController() 182 drive_sys.cpu.connectAllPorts(drive_sys.membus) 183 if options.fastmem: 184 drive_sys.cpu.fastmem = True 185 if options.kernel is not None: 186 drive_sys.kernel = binary(options.kernel) 187 188 if is_kvm_cpu(DriveCPUClass): 189 drive_sys.vm = KvmVM() 190 191 drive_sys.iobridge = Bridge(delay='50ns', 192 ranges = drive_sys.mem_ranges) 193 drive_sys.iobridge.slave = drive_sys.iobus.master 194 drive_sys.iobridge.master = drive_sys.membus.slave 195 196 drive_sys.init_param = options.init_param 197 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 198elif len(bm) == 1: 199 root = Root(full_system=True, system=test_sys) 200else: 201 print "Error I don't know how to create more than 2 systems." 202 sys.exit(1) 203 204if options.timesync: 205 root.time_sync_enable = True 206 207if options.frame_capture: 208 VncServer.frame_capture = True 209 210Simulation.setWorkCountOptions(test_sys, options) 211Simulation.run(options, root, test_sys, FutureClass)
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