1# Copyright (c) 2010 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright 21# notice, this list of conditions and the following disclaimer in the 22# documentation and/or other materials provided with the distribution; 23# neither the name of the copyright holders nor the names of its 24# contributors may be used to endorse or promote products derived from 25# this software without specific prior written permission. 26# 27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi 40 41import optparse 42import os 43import sys 44 45import m5 46from m5.defines import buildEnv 47from m5.objects import * 48from m5.util import addToPath, fatal 49 50if not buildEnv['FULL_SYSTEM']: 51 fatal("This script requires full-system mode (*_FS).") 52 53addToPath('../common') 54 55from FSConfig import * 56from SysPaths import * 57from Benchmarks import * 58import Simulation 59import CacheConfig 60from Caches import * 61 62# Get paths we might need. It's expected this file is in m5/configs/example. 63config_path = os.path.dirname(os.path.abspath(__file__)) 64config_root = os.path.dirname(config_path) 65 66parser = optparse.OptionParser() 67 68# Simulation options 69parser.add_option("--timesync", action="store_true", 70 help="Prevent simulated time from getting ahead of real time") 71 72# System options 73parser.add_option("--kernel", action="store", type="string") 74parser.add_option("--script", action="store", type="string") 75if buildEnv['TARGET_ISA'] == "arm": 76 parser.add_option("--bare-metal", action="store_true", 77 help="Provide the raw system without the linux specific bits") 78 parser.add_option("--machine-type", action="store", type="choice", 79 choices=ArmMachineType.map.keys(), default="RealView_PBX") 80# Benchmark options 81parser.add_option("--dual", action="store_true", 82 help="Simulate two systems attached with an ethernet link") 83parser.add_option("-b", "--benchmark", action="store", type="string", 84 dest="benchmark", 85 help="Specify the benchmark to run. Available benchmarks: %s"\ 86 % DefinedBenchmarks) 87 88# Metafile options 89parser.add_option("--etherdump", action="store", type="string", dest="etherdump", 90 help="Specify the filename to dump a pcap capture of the" \ 91 "ethernet traffic") 92 93execfile(os.path.join(config_root, "common", "Options.py")) 94 95(options, args) = parser.parse_args() 96 97if args: 98 print "Error: script doesn't take any positional arguments" 99 sys.exit(1) 100 101# driver system CPU is always simple... note this is an assignment of 102# a class, not an instance. 103DriveCPUClass = AtomicSimpleCPU 104drive_mem_mode = 'atomic' 105 106# system under test can be any CPU 107(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 108 109TestCPUClass.clock = '2GHz' 110DriveCPUClass.clock = '2GHz' 111 112if options.benchmark: 113 try: 114 bm = Benchmarks[options.benchmark] 115 except KeyError: 116 print "Error benchmark %s has not been defined." % options.benchmark 117 print "Valid benchmarks are: %s" % DefinedBenchmarks 118 sys.exit(1) 119else: 120 if options.dual: 121 bm = [SysConfig(), SysConfig()] 122 else: 123 bm = [SysConfig()] 124 125np = options.num_cpus 126 127if buildEnv['TARGET_ISA'] == "alpha": 128 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 129elif buildEnv['TARGET_ISA'] == "mips": 130 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 131elif buildEnv['TARGET_ISA'] == "sparc": 132 test_sys = makeSparcSystem(test_mem_mode, bm[0]) 133elif buildEnv['TARGET_ISA'] == "x86": 134 test_sys = makeLinuxX86System(test_mem_mode, np, bm[0]) 135elif buildEnv['TARGET_ISA'] == "arm": 136 test_sys = makeLinuxArmSystem(test_mem_mode, bm[0], 137 bare_metal=options.bare_metal, machine_type=options.machine_type) 138else: 139 fatal("incapable of building non-alpha or non-sparc full system!") 140 141if options.kernel is not None: 142 test_sys.kernel = binary(options.kernel) 143 144if options.script is not None: 145 test_sys.readfile = options.script 146 147test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 148 149CacheConfig.config_cache(options, test_sys) 150 151if options.caches or options.l2cache: 152 if bm[0]: 153 mem_size = bm[0].mem() 154 else: 155 mem_size = SysConfig().mem() 156 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 157 test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)] 158 test_sys.iocache = IOCache(addr_range=mem_size) 159 test_sys.iocache.cpu_side = test_sys.iobus.port 160 test_sys.iocache.mem_side = test_sys.membus.port 161 162for i in xrange(np): 163 if options.fastmem: 164 test_sys.cpu[i].physmem_port = test_sys.physmem.port 165 166if buildEnv['TARGET_ISA'] == 'mips': 167 setMipsOptions(TestCPUClass) 168 169if len(bm) == 2: 170 if buildEnv['TARGET_ISA'] == 'alpha': 171 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 172 elif buildEnv['TARGET_ISA'] == 'mips': 173 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 174 elif buildEnv['TARGET_ISA'] == 'sparc': 175 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 176 elif buildEnv['TARGET_ISA'] == 'x86': 177 drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 178 elif buildEnv['TARGET_ISA'] == 'arm': 179 drive_sys = makeLinuxArmSystem(drive_mem_mode, bm[1]) 180 drive_sys.cpu = DriveCPUClass(cpu_id=0)
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