1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright 9# notice, this list of conditions and the following disclaimer in the 10# documentation and/or other materials provided with the distribution; 11# neither the name of the copyright holders nor the names of its 12# contributors may be used to endorse or promote products derived from 13# this software without specific prior written permission. 14# 15# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 16# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 17# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 18# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 19# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 20# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 21# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 22# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 23# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 24# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 25# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 26# 27# Authors: Ali Saidi 28
|
29import optparse, os, sys
|
29import optparse 30import os 31import sys |
32 33import m5
|
34from m5.defines import buildEnv 35from m5.objects import * 36from m5.util import addToPath, fatal |
37
|
33if not m5.build_env['FULL_SYSTEM']:
34 m5.fatal("This script requires full-system mode (*_FS).")
|
38if not buildEnv['FULL_SYSTEM']: 39 fatal("This script requires full-system mode (*_FS).") |
40
|
36from m5.objects import *
37m5.AddToPath('../common')
|
41addToPath('../common') 42 |
43from FSConfig import * 44from SysPaths import * 45from Benchmarks import * 46import Simulation 47from Caches import * 48 49# Get paths we might need. It's expected this file is in m5/configs/example. 50config_path = os.path.dirname(os.path.abspath(__file__)) 51config_root = os.path.dirname(config_path) 52 53parser = optparse.OptionParser() 54 55# System options 56parser.add_option("--kernel", action="store", type="string") 57parser.add_option("--script", action="store", type="string") 58 59# Benchmark options 60parser.add_option("--dual", action="store_true", 61 help="Simulate two systems attached with an ethernet link") 62parser.add_option("-b", "--benchmark", action="store", type="string", 63 dest="benchmark", 64 help="Specify the benchmark to run. Available benchmarks: %s"\ 65 % DefinedBenchmarks) 66 67# Metafile options 68parser.add_option("--etherdump", action="store", type="string", dest="etherdump", 69 help="Specify the filename to dump a pcap capture of the" \ 70 "ethernet traffic") 71 72execfile(os.path.join(config_root, "common", "Options.py")) 73 74(options, args) = parser.parse_args() 75 76if args: 77 print "Error: script doesn't take any positional arguments" 78 sys.exit(1) 79 80# driver system CPU is always simple... note this is an assignment of 81# a class, not an instance. 82DriveCPUClass = AtomicSimpleCPU 83drive_mem_mode = 'atomic' 84 85# system under test can be any CPU 86(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 87 88TestCPUClass.clock = '2GHz' 89DriveCPUClass.clock = '2GHz' 90 91if options.benchmark: 92 try: 93 bm = Benchmarks[options.benchmark] 94 except KeyError: 95 print "Error benchmark %s has not been defined." % options.benchmark 96 print "Valid benchmarks are: %s" % DefinedBenchmarks 97 sys.exit(1) 98else: 99 if options.dual: 100 bm = [SysConfig(), SysConfig()] 101 else: 102 bm = [SysConfig()] 103 104np = options.num_cpus 105
|
101if m5.build_env['TARGET_ISA'] == "alpha":
|
106if buildEnv['TARGET_ISA'] == "alpha": |
107 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
|
103elif m5.build_env['TARGET_ISA'] == "mips":
|
108elif buildEnv['TARGET_ISA'] == "mips": |
109 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
|
105elif m5.build_env['TARGET_ISA'] == "sparc":
|
110elif buildEnv['TARGET_ISA'] == "sparc": |
111 test_sys = makeSparcSystem(test_mem_mode, bm[0])
|
107elif m5.build_env['TARGET_ISA'] == "x86":
|
112elif buildEnv['TARGET_ISA'] == "x86": |
113 test_sys = makeLinuxX86System(test_mem_mode, np, bm[0]) 114else:
|
110 m5.fatal("incapable of building non-alpha or non-sparc full system!")
|
115 fatal("incapable of building non-alpha or non-sparc full system!") |
116 117if options.kernel is not None: 118 test_sys.kernel = binary(options.kernel) 119 120if options.script is not None: 121 test_sys.readfile = options.script 122 123if options.l2cache: 124 test_sys.l2 = L2Cache(size = '2MB') 125 test_sys.tol2bus = Bus() 126 test_sys.l2.cpu_side = test_sys.tol2bus.port 127 test_sys.l2.mem_side = test_sys.membus.port 128 129test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 130 131if options.caches or options.l2cache: 132 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 133 test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] 134 test_sys.iocache = IOCache(addr_range=AddrRange(0, size='8GB')) 135 test_sys.iocache.cpu_side = test_sys.iobus.port 136 test_sys.iocache.mem_side = test_sys.membus.port 137 138for i in xrange(np): 139 if options.caches: 140 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 141 L1Cache(size = '64kB')) 142 if options.l2cache: 143 test_sys.cpu[i].connectMemPorts(test_sys.tol2bus) 144 else: 145 test_sys.cpu[i].connectMemPorts(test_sys.membus) 146 147 if options.fastmem: 148 test_sys.cpu[i].physmem_port = test_sys.physmem.port 149
|
145if m5.build_env['TARGET_ISA'] == 'mips':
|
150if buildEnv['TARGET_ISA'] == 'mips': |
151 setMipsOptions(TestCPUClass) 152 153if len(bm) == 2:
|
149 if m5.build_env['TARGET_ISA'] == 'alpha':
|
154 if buildEnv['TARGET_ISA'] == 'alpha': |
155 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
|
151 elif m5.build_env['TARGET_ISA'] == 'mips':
|
156 elif buildEnv['TARGET_ISA'] == 'mips': |
157 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
|
153 elif m5.build_env['TARGET_ISA'] == 'sparc':
|
158 elif buildEnv['TARGET_ISA'] == 'sparc': |
159 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
|
155 elif m5.build.env['TARGET_ISA'] == 'x86':
|
160 elif buildEnv['TARGET_ISA'] == 'x86': |
161 drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 162 drive_sys.cpu = DriveCPUClass(cpu_id=0) 163 drive_sys.cpu.connectMemPorts(drive_sys.membus) 164 if options.fastmem: 165 drive_sys.cpu.physmem_port = drive_sys.physmem.port 166 if options.kernel is not None: 167 drive_sys.kernel = binary(options.kernel) 168 169 root = makeDualRoot(test_sys, drive_sys, options.etherdump) 170elif len(bm) == 1: 171 root = Root(system=test_sys) 172else: 173 print "Error I don't know how to create more than 2 systems." 174 sys.exit(1) 175 176Simulation.run(options, root, test_sys, FutureClass)
|