1# Copyright (c) 2010-2013, 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42# Brad Beckmann
43
44import optparse
45import sys
46
47import m5
48from m5.defines import buildEnv
49from m5.objects import *
50from m5.util import addToPath, fatal
51
52addToPath('../')
53
54from ruby import Ruby
55
56from common.FSConfig import *
57from common.SysPaths import *
58from common.Benchmarks import *
59from common import Simulation
60from common import CacheConfig
61from common import MemConfig
62from common import CpuConfig
63from common.Caches import *
64from common import Options
65
66
67# Check if KVM support has been enabled, we might need to do VM
68# configuration if that's the case.
69have_kvm_support = 'BaseKvmCPU' in globals()
70def is_kvm_cpu(cpu_class):
71 return have_kvm_support and cpu_class != None and \
72 issubclass(cpu_class, BaseKvmCPU)
73
74def cmd_line_template():
75 if options.command_line and options.command_line_file:
76 print "Error: --command-line and --command-line-file are " \
77 "mutually exclusive"
78 sys.exit(1)
79 if options.command_line:
80 return options.command_line
81 if options.command_line_file:
82 return open(options.command_line_file).read().strip()
83 return None
84
85def build_test_system(np):
86 cmdline = cmd_line_template()
87 if buildEnv['TARGET_ISA'] == "alpha":
88 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
89 cmdline=cmdline)
90 elif buildEnv['TARGET_ISA'] == "mips":
91 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
92 elif buildEnv['TARGET_ISA'] == "sparc":
93 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
94 elif buildEnv['TARGET_ISA'] == "x86":
95 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
96 options.ruby, cmdline=cmdline)
97 elif buildEnv['TARGET_ISA'] == "arm":
98 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
99 options.num_cpus, bm[0], options.dtb_filename,
100 bare_metal=options.bare_metal,
101 cmdline=cmdline,
102 external_memory=options.external_memory_system,
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105 if options.enable_context_switch_stats_dump:
106 test_sys.enable_context_switch_stats_dump = True
107 else:
108 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
109
110 # Set the cache line size for the entire system
111 test_sys.cache_line_size = options.cacheline_size
112
113 # Create a top-level voltage domain
114 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
115
116 # Create a source clock for the system and set the clock period
117 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
118 voltage_domain = test_sys.voltage_domain)
119
120 # Create a CPU voltage domain
121 test_sys.cpu_voltage_domain = VoltageDomain()
122
123 # Create a source clock for the CPUs and set the clock period
124 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
125 voltage_domain =
126 test_sys.cpu_voltage_domain)
127
128 if options.kernel is not None:
129 test_sys.kernel = binary(options.kernel)
130
131 if options.script is not None:
132 test_sys.readfile = options.script
133
134 if options.lpae:
135 test_sys.have_lpae = True
136
137 if options.virtualisation:
138 test_sys.have_virtualization = True
139
140 test_sys.init_param = options.init_param
141
142 # For now, assign all the CPUs to the same clock domain
143 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
144 for i in xrange(np)]
145
146 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
147 test_sys.kvm_vm = KvmVM()
148
149 if options.ruby:
150 # Check for timing mode because ruby does not support atomic accesses
151 if not (options.cpu_type == "DerivO3CPU" or
152 options.cpu_type == "TimingSimpleCPU"):
153 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
154 sys.exit(1)
155
156 Ruby.create_system(options, True, test_sys, test_sys.iobus,
157 test_sys._dma_ports)
158
159 # Create a seperate clock domain for Ruby
160 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
161 voltage_domain = test_sys.voltage_domain)
162
163 # Connect the ruby io port to the PIO bus,
164 # assuming that there is just one such port.
165 test_sys.iobus.master = test_sys.ruby._io_port.slave
166
167 for (i, cpu) in enumerate(test_sys.cpu):
168 #
169 # Tie the cpu ports to the correct ruby system ports
170 #
171 cpu.clk_domain = test_sys.cpu_clk_domain
172 cpu.createThreads()
173 cpu.createInterruptController()
174
175 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
176 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
177
178 if buildEnv['TARGET_ISA'] in ("x86", "arm"):
179 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
180 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
181
182 if buildEnv['TARGET_ISA'] in "x86":
183 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
184 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
185 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
186
187 else:
188 if options.caches or options.l2cache:
189 # By default the IOCache runs at the system clock
190 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
191 test_sys.iocache.cpu_side = test_sys.iobus.master
192 test_sys.iocache.mem_side = test_sys.membus.slave
193 elif not options.external_memory_system:
194 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
195 test_sys.iobridge.slave = test_sys.iobus.master
196 test_sys.iobridge.master = test_sys.membus.slave
197
198 # Sanity check
199 if options.fastmem:
200 if TestCPUClass != AtomicSimpleCPU:
201 fatal("Fastmem can only be used with atomic CPU!")
202 if (options.caches or options.l2cache):
203 fatal("You cannot use fastmem in combination with caches!")
204
205 if options.simpoint_profile:
206 if not options.fastmem:
207 # Atomic CPU checked with fastmem option already
208 fatal("SimPoint generation should be done with atomic cpu and fastmem")
209 if np > 1:
210 fatal("SimPoint generation not supported with more than one CPUs")
211
212 for i in xrange(np):
213 if options.fastmem:
214 test_sys.cpu[i].fastmem = True
215 if options.simpoint_profile:
216 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
217 if options.checker:
218 test_sys.cpu[i].addCheckerCpu()
219 test_sys.cpu[i].createThreads()
220
221 # If elastic tracing is enabled when not restoring from checkpoint and
222 # when not fast forwarding using the atomic cpu, then check that the
223 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
224 # passes then attach the elastic trace probe.
225 # If restoring from checkpoint or fast forwarding, the code that does this for
226 # FutureCPUClass is in the Simulation module. If the check passes then the
227 # elastic trace probe is attached to the switch CPUs.
228 if options.elastic_trace_en and options.checkpoint_restore == None and \
229 not options.fast_forward:
230 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
231
232 CacheConfig.config_cache(options, test_sys)
233
234 MemConfig.config_mem(options, test_sys)
235
236 return test_sys
237
238def build_drive_system(np):
239 # driver system CPU is always simple, so is the memory
240 # Note this is an assignment of a class, not an instance.
241 DriveCPUClass = AtomicSimpleCPU
242 drive_mem_mode = 'atomic'
243 DriveMemClass = SimpleMemory
244
245 cmdline = cmd_line_template()
246 if buildEnv['TARGET_ISA'] == 'alpha':
247 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline)
248 elif buildEnv['TARGET_ISA'] == 'mips':
249 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
250 elif buildEnv['TARGET_ISA'] == 'sparc':
251 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
252 elif buildEnv['TARGET_ISA'] == 'x86':
253 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
254 cmdline=cmdline)
255 elif buildEnv['TARGET_ISA'] == 'arm':
256 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
257 bm[1], options.dtb_filename, cmdline=cmdline)
258
259 # Create a top-level voltage domain
260 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
261
262 # Create a source clock for the system and set the clock period
263 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
264 voltage_domain = drive_sys.voltage_domain)
265
266 # Create a CPU voltage domain
267 drive_sys.cpu_voltage_domain = VoltageDomain()
268
269 # Create a source clock for the CPUs and set the clock period
270 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
271 voltage_domain =
272 drive_sys.cpu_voltage_domain)
273
274 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
275 cpu_id=0)
276 drive_sys.cpu.createThreads()
277 drive_sys.cpu.createInterruptController()
278 drive_sys.cpu.connectAllPorts(drive_sys.membus)
279 if options.fastmem:
280 drive_sys.cpu.fastmem = True
281 if options.kernel is not None:
282 drive_sys.kernel = binary(options.kernel)
283
284 if is_kvm_cpu(DriveCPUClass):
285 drive_sys.kvm_vm = KvmVM()
286
287 drive_sys.iobridge = Bridge(delay='50ns',
288 ranges = drive_sys.mem_ranges)
289 drive_sys.iobridge.slave = drive_sys.iobus.master
290 drive_sys.iobridge.master = drive_sys.membus.slave
291
292 # Create the appropriate memory controllers and connect them to the
293 # memory bus
294 drive_sys.mem_ctrls = [DriveMemClass(range = r)
295 for r in drive_sys.mem_ranges]
296 for i in xrange(len(drive_sys.mem_ctrls)):
297 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
298
299 drive_sys.init_param = options.init_param
300
301 return drive_sys
302
303# Add options
304parser = optparse.OptionParser()
305Options.addCommonOptions(parser)
306Options.addFSOptions(parser)
307
308# Add the ruby specific and protocol specific options
309if '--ruby' in sys.argv:
310 Ruby.define_options(parser)
311
312(options, args) = parser.parse_args()
313
314if args:
315 print "Error: script doesn't take any positional arguments"
316 sys.exit(1)
317
318# system under test can be any CPU
319(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
320
321# Match the memories with the CPUs, based on the options for the test system
322TestMemClass = Simulation.setMemClass(options)
323
324if options.benchmark:
325 try:
326 bm = Benchmarks[options.benchmark]
327 except KeyError:
328 print "Error benchmark %s has not been defined." % options.benchmark
329 print "Valid benchmarks are: %s" % DefinedBenchmarks
330 sys.exit(1)
331else:
332 if options.dual:
333 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
334 mem=options.mem_size, os_type=options.os_type),
335 SysConfig(disk=options.disk_image, rootdev=options.root_device,
336 mem=options.mem_size, os_type=options.os_type)]
337 else:
338 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
339 mem=options.mem_size, os_type=options.os_type)]
340
341np = options.num_cpus
342
343test_sys = build_test_system(np)
344if len(bm) == 2:
345 drive_sys = build_drive_system(np)
346 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
347elif len(bm) == 1 and options.dist:
348 # This system is part of a dist-gem5 simulation
349 root = makeDistRoot(test_sys,
350 options.dist_rank,
351 options.dist_size,
352 options.dist_server_name,
353 options.dist_server_port,
354 options.dist_sync_repeat,
355 options.dist_sync_start,
356 options.ethernet_linkspeed,
357 options.ethernet_linkdelay,
358 options.etherdump);
359elif len(bm) == 1:
360 root = Root(full_system=True, system=test_sys)
361else:
362 print "Error I don't know how to create more than 2 systems."
363 sys.exit(1)
364
365if options.timesync:
366 root.time_sync_enable = True
367
368if options.frame_capture:
369 VncServer.frame_capture = True
370
371Simulation.setWorkCountOptions(test_sys, options)
372Simulation.run(options, root, test_sys, FutureClass)
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