1# Copyright (c) 2010-2013, 2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# 13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. 15# Copyright (c) 2006-2007 The Regents of The University of Michigan 16# All rights reserved. 17# 18# Redistribution and use in source and binary forms, with or without 19# modification, are permitted provided that the following conditions are 20# met: redistributions of source code must retain the above copyright 21# notice, this list of conditions and the following disclaimer; 22# redistributions in binary form must reproduce the above copyright 23# notice, this list of conditions and the following disclaimer in the 24# documentation and/or other materials provided with the distribution; 25# neither the name of the copyright holders nor the names of its 26# contributors may be used to endorse or promote products derived from 27# this software without specific prior written permission. 28# 29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS 30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT 31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR 32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT 33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, 34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40# 41# Authors: Ali Saidi 42# Brad Beckmann 43 44import optparse 45import sys 46 47import m5 48from m5.defines import buildEnv 49from m5.objects import * 50from m5.util import addToPath, fatal 51 52addToPath('../')
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64 65 66# Check if KVM support has been enabled, we might need to do VM 67# configuration if that's the case. 68have_kvm_support = 'BaseKvmCPU' in globals() 69def is_kvm_cpu(cpu_class): 70 return have_kvm_support and cpu_class != None and \ 71 issubclass(cpu_class, BaseKvmCPU) 72 73def cmd_line_template(): 74 if options.command_line and options.command_line_file: 75 print "Error: --command-line and --command-line-file are " \ 76 "mutually exclusive" 77 sys.exit(1) 78 if options.command_line: 79 return options.command_line 80 if options.command_line_file: 81 return open(options.command_line_file).read().strip() 82 return None 83 84def build_test_system(np): 85 cmdline = cmd_line_template() 86 if buildEnv['TARGET_ISA'] == "alpha": 87 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby, 88 cmdline=cmdline) 89 elif buildEnv['TARGET_ISA'] == "mips": 90 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline) 91 elif buildEnv['TARGET_ISA'] == "sparc": 92 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline) 93 elif buildEnv['TARGET_ISA'] == "x86": 94 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 95 options.ruby, cmdline=cmdline) 96 elif buildEnv['TARGET_ISA'] == "arm": 97 test_sys = makeArmSystem(test_mem_mode, options.machine_type, 98 options.num_cpus, bm[0], options.dtb_filename, 99 bare_metal=options.bare_metal, 100 cmdline=cmdline, 101 external_memory=options.external_memory_system, 102 ruby=options.ruby) 103 if options.enable_context_switch_stats_dump: 104 test_sys.enable_context_switch_stats_dump = True 105 else: 106 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 107 108 # Set the cache line size for the entire system 109 test_sys.cache_line_size = options.cacheline_size 110 111 # Create a top-level voltage domain 112 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 113 114 # Create a source clock for the system and set the clock period 115 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 116 voltage_domain = test_sys.voltage_domain) 117 118 # Create a CPU voltage domain 119 test_sys.cpu_voltage_domain = VoltageDomain() 120 121 # Create a source clock for the CPUs and set the clock period 122 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 123 voltage_domain = 124 test_sys.cpu_voltage_domain) 125 126 if options.kernel is not None: 127 test_sys.kernel = binary(options.kernel) 128 129 if options.script is not None: 130 test_sys.readfile = options.script 131 132 if options.lpae: 133 test_sys.have_lpae = True 134 135 if options.virtualisation: 136 test_sys.have_virtualization = True 137 138 test_sys.init_param = options.init_param 139 140 # For now, assign all the CPUs to the same clock domain 141 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 142 for i in xrange(np)] 143 144 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 145 test_sys.vm = KvmVM() 146 147 if options.ruby: 148 # Check for timing mode because ruby does not support atomic accesses 149 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 150 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 151 sys.exit(1) 152 153 Ruby.create_system(options, True, test_sys, test_sys.iobus, 154 test_sys._dma_ports) 155 156 # Create a seperate clock domain for Ruby 157 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 158 voltage_domain = test_sys.voltage_domain) 159 160 # Connect the ruby io port to the PIO bus, 161 # assuming that there is just one such port. 162 test_sys.iobus.master = test_sys.ruby._io_port.slave 163 164 for (i, cpu) in enumerate(test_sys.cpu): 165 # 166 # Tie the cpu ports to the correct ruby system ports 167 # 168 cpu.clk_domain = test_sys.cpu_clk_domain 169 cpu.createThreads() 170 cpu.createInterruptController() 171 172 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave 173 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave 174 175 if buildEnv['TARGET_ISA'] in ("x86", "arm"): 176 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave 177 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave 178 179 if buildEnv['TARGET_ISA'] in "x86": 180 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master 181 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave 182 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master 183 184 else: 185 if options.caches or options.l2cache: 186 # By default the IOCache runs at the system clock 187 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 188 test_sys.iocache.cpu_side = test_sys.iobus.master 189 test_sys.iocache.mem_side = test_sys.membus.slave 190 elif not options.external_memory_system: 191 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 192 test_sys.iobridge.slave = test_sys.iobus.master 193 test_sys.iobridge.master = test_sys.membus.slave 194 195 # Sanity check 196 if options.fastmem: 197 if TestCPUClass != AtomicSimpleCPU: 198 fatal("Fastmem can only be used with atomic CPU!") 199 if (options.caches or options.l2cache): 200 fatal("You cannot use fastmem in combination with caches!") 201 202 if options.simpoint_profile: 203 if not options.fastmem: 204 # Atomic CPU checked with fastmem option already 205 fatal("SimPoint generation should be done with atomic cpu and fastmem") 206 if np > 1: 207 fatal("SimPoint generation not supported with more than one CPUs") 208 209 for i in xrange(np): 210 if options.fastmem: 211 test_sys.cpu[i].fastmem = True 212 if options.simpoint_profile: 213 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval) 214 if options.checker: 215 test_sys.cpu[i].addCheckerCpu() 216 test_sys.cpu[i].createThreads() 217 218 # If elastic tracing is enabled when not restoring from checkpoint and 219 # when not fast forwarding using the atomic cpu, then check that the 220 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check 221 # passes then attach the elastic trace probe. 222 # If restoring from checkpoint or fast forwarding, the code that does this for 223 # FutureCPUClass is in the Simulation module. If the check passes then the 224 # elastic trace probe is attached to the switch CPUs. 225 if options.elastic_trace_en and options.checkpoint_restore == None and \ 226 not options.fast_forward: 227 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options) 228 229 CacheConfig.config_cache(options, test_sys) 230 231 MemConfig.config_mem(options, test_sys) 232 233 return test_sys 234 235def build_drive_system(np): 236 # driver system CPU is always simple, so is the memory 237 # Note this is an assignment of a class, not an instance. 238 DriveCPUClass = AtomicSimpleCPU 239 drive_mem_mode = 'atomic' 240 DriveMemClass = SimpleMemory 241 242 cmdline = cmd_line_template() 243 if buildEnv['TARGET_ISA'] == 'alpha': 244 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline) 245 elif buildEnv['TARGET_ISA'] == 'mips': 246 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline) 247 elif buildEnv['TARGET_ISA'] == 'sparc': 248 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline) 249 elif buildEnv['TARGET_ISA'] == 'x86': 250 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1], 251 cmdline=cmdline) 252 elif buildEnv['TARGET_ISA'] == 'arm': 253 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np, 254 bm[1], options.dtb_filename, cmdline=cmdline) 255 256 # Create a top-level voltage domain 257 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 258 259 # Create a source clock for the system and set the clock period 260 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 261 voltage_domain = drive_sys.voltage_domain) 262 263 # Create a CPU voltage domain 264 drive_sys.cpu_voltage_domain = VoltageDomain() 265 266 # Create a source clock for the CPUs and set the clock period 267 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock, 268 voltage_domain = 269 drive_sys.cpu_voltage_domain) 270 271 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain, 272 cpu_id=0) 273 drive_sys.cpu.createThreads() 274 drive_sys.cpu.createInterruptController() 275 drive_sys.cpu.connectAllPorts(drive_sys.membus) 276 if options.fastmem: 277 drive_sys.cpu.fastmem = True 278 if options.kernel is not None: 279 drive_sys.kernel = binary(options.kernel) 280 281 if is_kvm_cpu(DriveCPUClass): 282 drive_sys.vm = KvmVM() 283 284 drive_sys.iobridge = Bridge(delay='50ns', 285 ranges = drive_sys.mem_ranges) 286 drive_sys.iobridge.slave = drive_sys.iobus.master 287 drive_sys.iobridge.master = drive_sys.membus.slave 288 289 # Create the appropriate memory controllers and connect them to the 290 # memory bus 291 drive_sys.mem_ctrls = [DriveMemClass(range = r) 292 for r in drive_sys.mem_ranges] 293 for i in xrange(len(drive_sys.mem_ctrls)): 294 drive_sys.mem_ctrls[i].port = drive_sys.membus.master 295 296 drive_sys.init_param = options.init_param 297 298 return drive_sys 299 300# Add options 301parser = optparse.OptionParser() 302Options.addCommonOptions(parser) 303Options.addFSOptions(parser) 304 305# Add the ruby specific and protocol specific options 306if '--ruby' in sys.argv: 307 Ruby.define_options(parser) 308 309(options, args) = parser.parse_args() 310 311if args: 312 print "Error: script doesn't take any positional arguments" 313 sys.exit(1) 314 315# system under test can be any CPU 316(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options) 317 318# Match the memories with the CPUs, based on the options for the test system 319TestMemClass = Simulation.setMemClass(options) 320 321if options.benchmark: 322 try: 323 bm = Benchmarks[options.benchmark] 324 except KeyError: 325 print "Error benchmark %s has not been defined." % options.benchmark 326 print "Valid benchmarks are: %s" % DefinedBenchmarks 327 sys.exit(1) 328else: 329 if options.dual: 330 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 331 mem=options.mem_size, os_type=options.os_type), 332 SysConfig(disk=options.disk_image, rootdev=options.root_device, 333 mem=options.mem_size, os_type=options.os_type)] 334 else: 335 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device, 336 mem=options.mem_size, os_type=options.os_type)] 337 338np = options.num_cpus 339 340test_sys = build_test_system(np) 341if len(bm) == 2: 342 drive_sys = build_drive_system(np) 343 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump) 344elif len(bm) == 1 and options.dist: 345 # This system is part of a dist-gem5 simulation 346 root = makeDistRoot(test_sys, 347 options.dist_rank, 348 options.dist_size, 349 options.dist_server_name, 350 options.dist_server_port, 351 options.dist_sync_repeat, 352 options.dist_sync_start, 353 options.ethernet_linkspeed, 354 options.ethernet_linkdelay, 355 options.etherdump); 356elif len(bm) == 1: 357 root = Root(full_system=True, system=test_sys) 358else: 359 print "Error I don't know how to create more than 2 systems." 360 sys.exit(1) 361 362if options.timesync: 363 root.time_sync_enable = True 364 365if options.frame_capture: 366 VncServer.frame_capture = True 367 368Simulation.setWorkCountOptions(test_sys, options) 369Simulation.run(options, root, test_sys, FutureClass)
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