1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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97 if options.dual:
98 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
99 else:
100 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
101
102np = options.num_cpus
103
104if buildEnv['TARGET_ISA'] == "alpha":
105 test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0])
105 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
106elif buildEnv['TARGET_ISA'] == "mips":
107 test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0])
107 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
108elif buildEnv['TARGET_ISA'] == "sparc":
109 test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0])
109 test_sys = makeSparcSystem(test_mem_mode, bm[0])
110elif buildEnv['TARGET_ISA'] == "x86":
111 test_sys = makeLinuxX86System(test_mem_mode, TestMemClass,
112 options.num_cpus, bm[0])
111 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
112elif buildEnv['TARGET_ISA'] == "arm":
114 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
115 TestMemClass, bm[0], options.dtb_filename,
113 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
114 options.dtb_filename,
115 bare_metal=options.bare_metal)
116else:
117 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
118
119# Create a source clock for the system and set the clock period
120test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
121
122# Create a source clock for the CPUs and set the clock period

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158 if options.fastmem:
159 test_sys.cpu[i].fastmem = True
160 if options.checker:
161 test_sys.cpu[i].addCheckerCpu()
162 test_sys.cpu[i].createThreads()
163
164CacheConfig.config_cache(options, test_sys)
165
166# Create the appropriate memory controllers and connect them to the
167# memory bus
168test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True)
169 for r in test_sys.mem_ranges]
170for i in xrange(len(test_sys.mem_ctrls)):
171 test_sys.mem_ctrls[i].port = test_sys.membus.master
172
173if len(bm) == 2:
174 if buildEnv['TARGET_ISA'] == 'alpha':
169 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, bm[1])
175 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
176 elif buildEnv['TARGET_ISA'] == 'mips':
171 drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, bm[1])
177 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
178 elif buildEnv['TARGET_ISA'] == 'sparc':
173 drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1])
179 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
180 elif buildEnv['TARGET_ISA'] == 'x86':
175 drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1])
181 drive_sys = makeX86System(drive_mem_mode, np, bm[1])
182 elif buildEnv['TARGET_ISA'] == 'arm':
177 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
178 DriveMemClass, bm[1])
183 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
184
185 # Create a source clock for the system and set the clock period
186 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
187
188 # Create a source clock for the CPUs and set the clock period
189 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
190
191 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,

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201 if is_kvm_cpu(DriveCPUClass):
202 drive_sys.vm = KvmVM()
203
204 drive_sys.iobridge = Bridge(delay='50ns',
205 ranges = drive_sys.mem_ranges)
206 drive_sys.iobridge.slave = drive_sys.iobus.master
207 drive_sys.iobridge.master = drive_sys.membus.slave
208
209 # Create the appropriate memory controllers and connect them to the
210 # memory bus
211 drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True)
212 for r in drive_sys.mem_ranges]
213 for i in xrange(len(drive_sys.mem_ctrls)):
214 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
215
216 drive_sys.init_param = options.init_param
217 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
218elif len(bm) == 1:
219 root = Root(full_system=True, system=test_sys)
220else:
221 print "Error I don't know how to create more than 2 systems."
222 sys.exit(1)
223
224if options.timesync:
225 root.time_sync_enable = True
226
227if options.frame_capture:
228 VncServer.frame_capture = True
229
230Simulation.setWorkCountOptions(test_sys, options)
231Simulation.run(options, root, test_sys, FutureClass)