1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 114 unchanged lines hidden (view full) --- 123 test_sys.iocache.cpu_side = test_sys.iobus.master 124 test_sys.iocache.mem_side = test_sys.membus.slave 125else: 126 test_sys.iobridge = Bridge(delay='50ns', ranges = [test_sys.physmem.range]) 127 test_sys.iobridge.slave = test_sys.iobus.master 128 test_sys.iobridge.master = test_sys.membus.slave 129 130# Sanity check |
131if options.fastmem: 132 if TestCPUClass != AtomicSimpleCPU: 133 fatal("Fastmem can only be used with atomic CPU!") 134 if (options.caches or options.l2cache): 135 fatal("You cannot use fastmem in combination with caches!") |
136 137for i in xrange(np): 138 if options.fastmem: 139 test_sys.cpu[i].fastmem = True 140 if options.checker: 141 test_sys.cpu[i].addCheckerCpu() 142 143CacheConfig.config_cache(options, test_sys) --- 41 unchanged lines hidden --- |