1# Copyright (c) 2006-2007 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 112 unchanged lines hidden (view full) --- 121 test_sys.l2.cpu_side = test_sys.tol2bus.port 122 test_sys.l2.mem_side = test_sys.membus.port 123 124test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 125 126if options.caches: 127 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)] 128 test_sys.bridge.filter_ranges_b=[AddrRange(0, size='8GB')] |
129 test_sys.iocache = IOCache(addr_range=AddrRange(0, size='8GB')) |
130 test_sys.iocache.cpu_side = test_sys.iobus.port 131 test_sys.iocache.mem_side = test_sys.membus.port 132 133for i in xrange(np): 134 if options.caches: 135 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 136 L1Cache(size = '64kB')) 137 if options.l2cache: --- 34 unchanged lines hidden --- |