1# Copyright (c) 2006 The Regents of The University of Michigan 2# All rights reserved. 3# 4# Redistribution and use in source and binary forms, with or without 5# modification, are permitted provided that the following conditions are 6# met: redistributions of source code must retain the above copyright 7# notice, this list of conditions and the following disclaimer; 8# redistributions in binary form must reproduce the above copyright --- 33 unchanged lines hidden (view full) --- 42 43# Get paths we might need. It's expected this file is in m5/configs/example. 44config_path = os.path.dirname(os.path.abspath(__file__)) 45config_root = os.path.dirname(config_path) 46 47parser = optparse.OptionParser() 48 49# Benchmark options |
50parser.add_option("--l2cache", action="store_true") |
51parser.add_option("--dual", action="store_true", 52 help="Simulate two systems attached with an ethernet link") 53parser.add_option("-b", "--benchmark", action="store", type="string", 54 dest="benchmark", 55 help="Specify the benchmark to run. Available benchmarks: %s"\ 56 % DefinedBenchmarks) 57 58# Metafile options --- 30 unchanged lines hidden (view full) --- 89else: 90 if options.dual: 91 bm = [SysConfig(), SysConfig()] 92 else: 93 bm = [SysConfig()] 94 95test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) 96np = options.num_cpus |
97 98if options.l2cache: 99 test_sys.l2 = L2Cache(size = '2MB') 100 test_sys.tol2bus = Bus() 101 test_sys.l2.cpu_side = test_sys.tol2bus.port 102 test_sys.l2.mem_side = test_sys.membus.port 103 |
104test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 105for i in xrange(np): 106 if options.caches: 107 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'), 108 L1Cache(size = '64kB')) |
109 |
110 if options.l2cache: 111 test_sys.cpu[i].connectMemPorts(test_sys.tol2bus) 112 else: 113 test_sys.cpu[i].connectMemPorts(test_sys.membus) 114 |
115if len(bm) == 2: 116 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 117 drive_sys.cpu = DriveCPUClass(cpu_id=0) 118 drive_sys.cpu.connectMemPorts(drive_sys.membus) 119 root = makeDualRoot(test_sys, drive_sys, options.etherdump) 120elif len(bm) == 1: 121 root = Root(clock = '1THz', system = test_sys) 122else: 123 print "Error I don't know how to create more than 2 systems." 124 sys.exit(1) 125 126Simulation.run(options, root, test_sys, FutureClass) |