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< # Copyright (c) 2010 ARM Limited
---
> # Copyright (c) 2010-2011 ARM Limited
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> if bm[0]:
> mem_size = bm[0].mem()
> else:
> mem_size = SysConfig().mem()
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< if bm[0]:
< mem_size = bm[0].mem()
< else:
< mem_size = SysConfig().mem()
< # For x86, we need to poke a hole for interrupt messages to get back to the
< # CPU. These use a portion of the physical address space which has a
< # non-zero prefix in the top nibble. Normal memory accesses have a 0
< # prefix.
< if buildEnv['TARGET_ISA'] == 'x86':
< test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)]
< else:
< test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
< test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)]
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> else:
> test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
> ranges = [AddrRange(0, mem_size)])
> test_sys.iobridge.slave = test_sys.iobus.port
> test_sys.iobridge.master = test_sys.membus.port