49a50
> parser.add_option("--l2cache", action="store_true")
95a97,103
>
> if options.l2cache:
> test_sys.l2 = L2Cache(size = '2MB')
> test_sys.tol2bus = Bus()
> test_sys.l2.cpu_side = test_sys.tol2bus.port
> test_sys.l2.mem_side = test_sys.membus.port
>
101d108
< test_sys.cpu[i].connectMemPorts(test_sys.membus)
102a110,114
> if options.l2cache:
> test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
> else:
> test_sys.cpu[i].connectMemPorts(test_sys.membus)
>