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< # system under test can be any of these CPUs
< if options.detailed:
< TestCPUClass = DerivO3CPU
< test_mem_mode = 'timing'
< elif options.timing:
< TestCPUClass = TimingSimpleCPU
< test_mem_mode = 'timing'
< else:
< TestCPUClass = AtomicSimpleCPU
< test_mem_mode = 'atomic'
---
> # system under test can be any CPU
> (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
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< if options.caches and not options.standard_switch:
---
> if options.caches and not options.standard_switch and not FutureClass:
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< Simulation.run(options, root, test_sys)
---
> Simulation.run(options, root, test_sys, FutureClass)