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< Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
---
> Ruby.create_system(options, True, test_sys, test_sys.iobus,
> test_sys._dma_ports)
> test_sys.physmem = [SimpleMemory(range = r, null = True)
> for r in test_sys.mem_ranges]
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< test_sys.ruby._cpu_ports[i].access_phys_mem = True
---
> # Connect the ruby io port to the PIO bus,
> # assuming that there is just one such port.
> test_sys.iobus.master = test_sys.ruby._io_port.slave
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< # Create the appropriate memory controllers
< # and connect them to the IO bus
< test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
< for i in xrange(len(test_sys.mem_ctrls)):
< test_sys.mem_ctrls[i].port = test_sys.iobus.master
<