66,68d65
< parser = optparse.OptionParser()
< Options.addCommonOptions(parser)
< Options.addFSOptions(parser)
70,84d66
< # Add the ruby specific and protocol specific options
< if '--ruby' in sys.argv:
< Ruby.define_options(parser)
<
< (options, args) = parser.parse_args()
<
< if args:
< print "Error: script doesn't take any positional arguments"
< sys.exit(1)
<
< # driver system CPU is always simple... note this is an assignment of
< # a class, not an instance.
< DriveCPUClass = AtomicSimpleCPU
< drive_mem_mode = 'atomic'
<
92,110c74,89
< # system under test can be any CPU
< (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
<
< # Match the memories with the CPUs, the driver system always simple,
< # and based on the options for the test system
< DriveMemClass = SimpleMemory
< TestMemClass = Simulation.setMemClass(options)
<
< if options.benchmark:
< try:
< bm = Benchmarks[options.benchmark]
< except KeyError:
< print "Error benchmark %s has not been defined." % options.benchmark
< print "Valid benchmarks are: %s" % DefinedBenchmarks
< sys.exit(1)
< else:
< if options.dual:
< bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
< SysConfig(disk=options.disk_image, mem=options.mem_size)]
---
> def build_test_system(np):
> if buildEnv['TARGET_ISA'] == "alpha":
> test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
> elif buildEnv['TARGET_ISA'] == "mips":
> test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
> elif buildEnv['TARGET_ISA'] == "sparc":
> test_sys = makeSparcSystem(test_mem_mode, bm[0])
> elif buildEnv['TARGET_ISA'] == "x86":
> test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
> options.ruby)
> elif buildEnv['TARGET_ISA'] == "arm":
> test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
> options.dtb_filename,
> bare_metal=options.bare_metal)
> if options.enable_context_switch_stats_dump:
> test_sys.enable_context_switch_stats_dump = True
112c91
< bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
---
> fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
114c93,94
< np = options.num_cpus
---
> # Set the cache line size for the entire system
> test_sys.cache_line_size = options.cacheline_size
116,132c96,97
< if buildEnv['TARGET_ISA'] == "alpha":
< test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
< elif buildEnv['TARGET_ISA'] == "mips":
< test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
< elif buildEnv['TARGET_ISA'] == "sparc":
< test_sys = makeSparcSystem(test_mem_mode, bm[0])
< elif buildEnv['TARGET_ISA'] == "x86":
< test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
< options.ruby)
< elif buildEnv['TARGET_ISA'] == "arm":
< test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
< options.dtb_filename,
< bare_metal=options.bare_metal)
< if options.enable_context_switch_stats_dump:
< test_sys.enable_context_switch_stats_dump = True
< else:
< fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
---
> # Create a top-level voltage domain
> test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
134,135c99,101
< # Set the cache line size for the entire system
< test_sys.cache_line_size = options.cacheline_size
---
> # Create a source clock for the system and set the clock period
> test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
> voltage_domain = test_sys.voltage_domain)
137,138c103,104
< # Create a top-level voltage domain
< test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
---
> # Create a CPU voltage domain
> test_sys.cpu_voltage_domain = VoltageDomain()
140,142c106,109
< # Create a source clock for the system and set the clock period
< test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
< voltage_domain = test_sys.voltage_domain)
---
> # Create a source clock for the CPUs and set the clock period
> test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
> voltage_domain =
> test_sys.cpu_voltage_domain)
144,145c111,112
< # Create a CPU voltage domain
< test_sys.cpu_voltage_domain = VoltageDomain()
---
> if options.kernel is not None:
> test_sys.kernel = binary(options.kernel)
147,150c114,115
< # Create a source clock for the CPUs and set the clock period
< test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
< voltage_domain =
< test_sys.cpu_voltage_domain)
---
> if options.script is not None:
> test_sys.readfile = options.script
152,153c117,118
< if options.kernel is not None:
< test_sys.kernel = binary(options.kernel)
---
> if options.lpae:
> test_sys.have_lpae = True
155,156c120,121
< if options.script is not None:
< test_sys.readfile = options.script
---
> if options.virtualisation:
> test_sys.have_virtualization = True
158,159c123
< if options.lpae:
< test_sys.have_lpae = True
---
> test_sys.init_param = options.init_param
161,162c125,127
< if options.virtualisation:
< test_sys.have_virtualization = True
---
> # For now, assign all the CPUs to the same clock domain
> test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
> for i in xrange(np)]
164c129,130
< test_sys.init_param = options.init_param
---
> if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
> test_sys.vm = KvmVM()
166,168c132,136
< # For now, assign all the CPUs to the same clock domain
< test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
< for i in xrange(np)]
---
> if options.ruby:
> # Check for timing mode because ruby does not support atomic accesses
> if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
> print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
> sys.exit(1)
170,171c138
< if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
< test_sys.vm = KvmVM()
---
> Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
173,177c140,142
< if options.ruby:
< # Check for timing mode because ruby does not support atomic accesses
< if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
< print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
< sys.exit(1)
---
> # Create a seperate clock domain for Ruby
> test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
> voltage_domain = test_sys.voltage_domain)
179c144,150
< Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
---
> for (i, cpu) in enumerate(test_sys.cpu):
> #
> # Tie the cpu ports to the correct ruby system ports
> #
> cpu.clk_domain = test_sys.cpu_clk_domain
> cpu.createThreads()
> cpu.createInterruptController()
181,183c152,153
< # Create a seperate clock domain for Ruby
< test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
< voltage_domain = test_sys.voltage_domain)
---
> cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
> cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
185,191c155,157
< for (i, cpu) in enumerate(test_sys.cpu):
< #
< # Tie the cpu ports to the correct ruby system ports
< #
< cpu.clk_domain = test_sys.cpu_clk_domain
< cpu.createThreads()
< cpu.createInterruptController()
---
> if buildEnv['TARGET_ISA'] == "x86":
> cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
> cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
193,194c159,161
< cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
< cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
---
> cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
> cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
> cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
196,198c163
< if buildEnv['TARGET_ISA'] == "x86":
< cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
< cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
---
> test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
200,202c165,169
< cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
< cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
< cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
---
> # Create the appropriate memory controllers
> # and connect them to the IO bus
> test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
> for i in xrange(len(test_sys.mem_ctrls)):
> test_sys.mem_ctrls[i].port = test_sys.iobus.master
204c171,180
< test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
---
> else:
> if options.caches or options.l2cache:
> # By default the IOCache runs at the system clock
> test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
> test_sys.iocache.cpu_side = test_sys.iobus.master
> test_sys.iocache.mem_side = test_sys.membus.slave
> else:
> test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
> test_sys.iobridge.slave = test_sys.iobus.master
> test_sys.iobridge.master = test_sys.membus.slave
206,210c182,187
< # Create the appropriate memory controllers and connect them to the
< # PIO bus
< test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
< for i in xrange(len(test_sys.mem_ctrls)):
< test_sys.mem_ctrls[i].port = test_sys.iobus.master
---
> # Sanity check
> if options.fastmem:
> if TestCPUClass != AtomicSimpleCPU:
> fatal("Fastmem can only be used with atomic CPU!")
> if (options.caches or options.l2cache):
> fatal("You cannot use fastmem in combination with caches!")
212,221c189,194
< else:
< if options.caches or options.l2cache:
< # By default the IOCache runs at the system clock
< test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
< test_sys.iocache.cpu_side = test_sys.iobus.master
< test_sys.iocache.mem_side = test_sys.membus.slave
< else:
< test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
< test_sys.iobridge.slave = test_sys.iobus.master
< test_sys.iobridge.master = test_sys.membus.slave
---
> for i in xrange(np):
> if options.fastmem:
> test_sys.cpu[i].fastmem = True
> if options.checker:
> test_sys.cpu[i].addCheckerCpu()
> test_sys.cpu[i].createThreads()
223,228c196,197
< # Sanity check
< if options.fastmem:
< if TestCPUClass != AtomicSimpleCPU:
< fatal("Fastmem can only be used with atomic CPU!")
< if (options.caches or options.l2cache):
< fatal("You cannot use fastmem in combination with caches!")
---
> CacheConfig.config_cache(options, test_sys)
> MemConfig.config_mem(options, test_sys)
230,235c199
< for i in xrange(np):
< if options.fastmem:
< test_sys.cpu[i].fastmem = True
< if options.checker:
< test_sys.cpu[i].addCheckerCpu()
< test_sys.cpu[i].createThreads()
---
> return test_sys
237,238c201,206
< CacheConfig.config_cache(options, test_sys)
< MemConfig.config_mem(options, test_sys)
---
> def build_drive_system(np):
> # driver system CPU is always simple, so is the memory
> # Note this is an assignment of a class, not an instance.
> DriveCPUClass = AtomicSimpleCPU
> drive_mem_mode = 'atomic'
> DriveMemClass = SimpleMemory
240d207
< if len(bm) == 2:
256c223,224
< drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
---
> drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
> voltage_domain = drive_sys.voltage_domain)
291a260,302
>
> return drive_sys
>
> # Add options
> parser = optparse.OptionParser()
> Options.addCommonOptions(parser)
> Options.addFSOptions(parser)
>
> # Add the ruby specific and protocol specific options
> if '--ruby' in sys.argv:
> Ruby.define_options(parser)
>
> (options, args) = parser.parse_args()
>
> if args:
> print "Error: script doesn't take any positional arguments"
> sys.exit(1)
>
> # system under test can be any CPU
> (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
>
> # Match the memories with the CPUs, based on the options for the test system
> TestMemClass = Simulation.setMemClass(options)
>
> if options.benchmark:
> try:
> bm = Benchmarks[options.benchmark]
> except KeyError:
> print "Error benchmark %s has not been defined." % options.benchmark
> print "Valid benchmarks are: %s" % DefinedBenchmarks
> sys.exit(1)
> else:
> if options.dual:
> bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
> SysConfig(disk=options.disk_image, mem=options.mem_size)]
> else:
> bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
>
> np = options.num_cpus
>
> test_sys = build_test_system(np)
> if len(bm) == 2:
> drive_sys = build_drive_system(np)
< parser = optparse.OptionParser()
< Options.addCommonOptions(parser)
< Options.addFSOptions(parser)
70,84d66
< # Add the ruby specific and protocol specific options
< if '--ruby' in sys.argv:
< Ruby.define_options(parser)
<
< (options, args) = parser.parse_args()
<
< if args:
< print "Error: script doesn't take any positional arguments"
< sys.exit(1)
<
< # driver system CPU is always simple... note this is an assignment of
< # a class, not an instance.
< DriveCPUClass = AtomicSimpleCPU
< drive_mem_mode = 'atomic'
<
92,110c74,89
< # system under test can be any CPU
< (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
<
< # Match the memories with the CPUs, the driver system always simple,
< # and based on the options for the test system
< DriveMemClass = SimpleMemory
< TestMemClass = Simulation.setMemClass(options)
<
< if options.benchmark:
< try:
< bm = Benchmarks[options.benchmark]
< except KeyError:
< print "Error benchmark %s has not been defined." % options.benchmark
< print "Valid benchmarks are: %s" % DefinedBenchmarks
< sys.exit(1)
< else:
< if options.dual:
< bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
< SysConfig(disk=options.disk_image, mem=options.mem_size)]
---
> def build_test_system(np):
> if buildEnv['TARGET_ISA'] == "alpha":
> test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
> elif buildEnv['TARGET_ISA'] == "mips":
> test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
> elif buildEnv['TARGET_ISA'] == "sparc":
> test_sys = makeSparcSystem(test_mem_mode, bm[0])
> elif buildEnv['TARGET_ISA'] == "x86":
> test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
> options.ruby)
> elif buildEnv['TARGET_ISA'] == "arm":
> test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
> options.dtb_filename,
> bare_metal=options.bare_metal)
> if options.enable_context_switch_stats_dump:
> test_sys.enable_context_switch_stats_dump = True
112c91
< bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
---
> fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
114c93,94
< np = options.num_cpus
---
> # Set the cache line size for the entire system
> test_sys.cache_line_size = options.cacheline_size
116,132c96,97
< if buildEnv['TARGET_ISA'] == "alpha":
< test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
< elif buildEnv['TARGET_ISA'] == "mips":
< test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
< elif buildEnv['TARGET_ISA'] == "sparc":
< test_sys = makeSparcSystem(test_mem_mode, bm[0])
< elif buildEnv['TARGET_ISA'] == "x86":
< test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
< options.ruby)
< elif buildEnv['TARGET_ISA'] == "arm":
< test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
< options.dtb_filename,
< bare_metal=options.bare_metal)
< if options.enable_context_switch_stats_dump:
< test_sys.enable_context_switch_stats_dump = True
< else:
< fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
---
> # Create a top-level voltage domain
> test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
134,135c99,101
< # Set the cache line size for the entire system
< test_sys.cache_line_size = options.cacheline_size
---
> # Create a source clock for the system and set the clock period
> test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
> voltage_domain = test_sys.voltage_domain)
137,138c103,104
< # Create a top-level voltage domain
< test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
---
> # Create a CPU voltage domain
> test_sys.cpu_voltage_domain = VoltageDomain()
140,142c106,109
< # Create a source clock for the system and set the clock period
< test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
< voltage_domain = test_sys.voltage_domain)
---
> # Create a source clock for the CPUs and set the clock period
> test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
> voltage_domain =
> test_sys.cpu_voltage_domain)
144,145c111,112
< # Create a CPU voltage domain
< test_sys.cpu_voltage_domain = VoltageDomain()
---
> if options.kernel is not None:
> test_sys.kernel = binary(options.kernel)
147,150c114,115
< # Create a source clock for the CPUs and set the clock period
< test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
< voltage_domain =
< test_sys.cpu_voltage_domain)
---
> if options.script is not None:
> test_sys.readfile = options.script
152,153c117,118
< if options.kernel is not None:
< test_sys.kernel = binary(options.kernel)
---
> if options.lpae:
> test_sys.have_lpae = True
155,156c120,121
< if options.script is not None:
< test_sys.readfile = options.script
---
> if options.virtualisation:
> test_sys.have_virtualization = True
158,159c123
< if options.lpae:
< test_sys.have_lpae = True
---
> test_sys.init_param = options.init_param
161,162c125,127
< if options.virtualisation:
< test_sys.have_virtualization = True
---
> # For now, assign all the CPUs to the same clock domain
> test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
> for i in xrange(np)]
164c129,130
< test_sys.init_param = options.init_param
---
> if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
> test_sys.vm = KvmVM()
166,168c132,136
< # For now, assign all the CPUs to the same clock domain
< test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
< for i in xrange(np)]
---
> if options.ruby:
> # Check for timing mode because ruby does not support atomic accesses
> if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
> print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
> sys.exit(1)
170,171c138
< if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
< test_sys.vm = KvmVM()
---
> Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
173,177c140,142
< if options.ruby:
< # Check for timing mode because ruby does not support atomic accesses
< if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
< print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
< sys.exit(1)
---
> # Create a seperate clock domain for Ruby
> test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
> voltage_domain = test_sys.voltage_domain)
179c144,150
< Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
---
> for (i, cpu) in enumerate(test_sys.cpu):
> #
> # Tie the cpu ports to the correct ruby system ports
> #
> cpu.clk_domain = test_sys.cpu_clk_domain
> cpu.createThreads()
> cpu.createInterruptController()
181,183c152,153
< # Create a seperate clock domain for Ruby
< test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
< voltage_domain = test_sys.voltage_domain)
---
> cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
> cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
185,191c155,157
< for (i, cpu) in enumerate(test_sys.cpu):
< #
< # Tie the cpu ports to the correct ruby system ports
< #
< cpu.clk_domain = test_sys.cpu_clk_domain
< cpu.createThreads()
< cpu.createInterruptController()
---
> if buildEnv['TARGET_ISA'] == "x86":
> cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
> cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
193,194c159,161
< cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
< cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
---
> cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
> cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
> cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
196,198c163
< if buildEnv['TARGET_ISA'] == "x86":
< cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
< cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
---
> test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
200,202c165,169
< cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
< cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
< cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
---
> # Create the appropriate memory controllers
> # and connect them to the IO bus
> test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
> for i in xrange(len(test_sys.mem_ctrls)):
> test_sys.mem_ctrls[i].port = test_sys.iobus.master
204c171,180
< test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
---
> else:
> if options.caches or options.l2cache:
> # By default the IOCache runs at the system clock
> test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
> test_sys.iocache.cpu_side = test_sys.iobus.master
> test_sys.iocache.mem_side = test_sys.membus.slave
> else:
> test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
> test_sys.iobridge.slave = test_sys.iobus.master
> test_sys.iobridge.master = test_sys.membus.slave
206,210c182,187
< # Create the appropriate memory controllers and connect them to the
< # PIO bus
< test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
< for i in xrange(len(test_sys.mem_ctrls)):
< test_sys.mem_ctrls[i].port = test_sys.iobus.master
---
> # Sanity check
> if options.fastmem:
> if TestCPUClass != AtomicSimpleCPU:
> fatal("Fastmem can only be used with atomic CPU!")
> if (options.caches or options.l2cache):
> fatal("You cannot use fastmem in combination with caches!")
212,221c189,194
< else:
< if options.caches or options.l2cache:
< # By default the IOCache runs at the system clock
< test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
< test_sys.iocache.cpu_side = test_sys.iobus.master
< test_sys.iocache.mem_side = test_sys.membus.slave
< else:
< test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
< test_sys.iobridge.slave = test_sys.iobus.master
< test_sys.iobridge.master = test_sys.membus.slave
---
> for i in xrange(np):
> if options.fastmem:
> test_sys.cpu[i].fastmem = True
> if options.checker:
> test_sys.cpu[i].addCheckerCpu()
> test_sys.cpu[i].createThreads()
223,228c196,197
< # Sanity check
< if options.fastmem:
< if TestCPUClass != AtomicSimpleCPU:
< fatal("Fastmem can only be used with atomic CPU!")
< if (options.caches or options.l2cache):
< fatal("You cannot use fastmem in combination with caches!")
---
> CacheConfig.config_cache(options, test_sys)
> MemConfig.config_mem(options, test_sys)
230,235c199
< for i in xrange(np):
< if options.fastmem:
< test_sys.cpu[i].fastmem = True
< if options.checker:
< test_sys.cpu[i].addCheckerCpu()
< test_sys.cpu[i].createThreads()
---
> return test_sys
237,238c201,206
< CacheConfig.config_cache(options, test_sys)
< MemConfig.config_mem(options, test_sys)
---
> def build_drive_system(np):
> # driver system CPU is always simple, so is the memory
> # Note this is an assignment of a class, not an instance.
> DriveCPUClass = AtomicSimpleCPU
> drive_mem_mode = 'atomic'
> DriveMemClass = SimpleMemory
240d207
< if len(bm) == 2:
256c223,224
< drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
---
> drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
> voltage_domain = drive_sys.voltage_domain)
291a260,302
>
> return drive_sys
>
> # Add options
> parser = optparse.OptionParser()
> Options.addCommonOptions(parser)
> Options.addFSOptions(parser)
>
> # Add the ruby specific and protocol specific options
> if '--ruby' in sys.argv:
> Ruby.define_options(parser)
>
> (options, args) = parser.parse_args()
>
> if args:
> print "Error: script doesn't take any positional arguments"
> sys.exit(1)
>
> # system under test can be any CPU
> (TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
>
> # Match the memories with the CPUs, based on the options for the test system
> TestMemClass = Simulation.setMemClass(options)
>
> if options.benchmark:
> try:
> bm = Benchmarks[options.benchmark]
> except KeyError:
> print "Error benchmark %s has not been defined." % options.benchmark
> print "Valid benchmarks are: %s" % DefinedBenchmarks
> sys.exit(1)
> else:
> if options.dual:
> bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
> SysConfig(disk=options.disk_image, mem=options.mem_size)]
> else:
> bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
>
> np = options.num_cpus
>
> test_sys = build_test_system(np)
> if len(bm) == 2:
> drive_sys = build_drive_system(np)