1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40
41import optparse
42import sys
43
44import m5
45from m5.defines import buildEnv
46from m5.objects import *
47from m5.util import addToPath, fatal
48
49addToPath('../common')
50
51from FSConfig import *
52from SysPaths import *
53from Benchmarks import *
54import Simulation
55import CacheConfig
56from Caches import *
57import Options
58
59parser = optparse.OptionParser()
60Options.addCommonOptions(parser)
61Options.addFSOptions(parser)
62
63(options, args) = parser.parse_args()
64
65if args:
66 print "Error: script doesn't take any positional arguments"
67 sys.exit(1)
68
69# driver system CPU is always simple... note this is an assignment of
70# a class, not an instance.
71DriveCPUClass = AtomicSimpleCPU
72drive_mem_mode = 'atomic'
73
74# Check if KVM support has been enabled, we might need to do VM
75# configuration if that's the case.
76have_kvm_support = 'BaseKvmCPU' in globals()
77def is_kvm_cpu(cpu_class):
78 return have_kvm_support and cpu_class != None and \
79 issubclass(cpu_class, BaseKvmCPU)
80
81# system under test can be any CPU
82(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
83
84TestCPUClass.clock = options.clock
85DriveCPUClass.clock = options.clock
86
| 1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40
41import optparse
42import sys
43
44import m5
45from m5.defines import buildEnv
46from m5.objects import *
47from m5.util import addToPath, fatal
48
49addToPath('../common')
50
51from FSConfig import *
52from SysPaths import *
53from Benchmarks import *
54import Simulation
55import CacheConfig
56from Caches import *
57import Options
58
59parser = optparse.OptionParser()
60Options.addCommonOptions(parser)
61Options.addFSOptions(parser)
62
63(options, args) = parser.parse_args()
64
65if args:
66 print "Error: script doesn't take any positional arguments"
67 sys.exit(1)
68
69# driver system CPU is always simple... note this is an assignment of
70# a class, not an instance.
71DriveCPUClass = AtomicSimpleCPU
72drive_mem_mode = 'atomic'
73
74# Check if KVM support has been enabled, we might need to do VM
75# configuration if that's the case.
76have_kvm_support = 'BaseKvmCPU' in globals()
77def is_kvm_cpu(cpu_class):
78 return have_kvm_support and cpu_class != None and \
79 issubclass(cpu_class, BaseKvmCPU)
80
81# system under test can be any CPU
82(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
83
84TestCPUClass.clock = options.clock
85DriveCPUClass.clock = options.clock
86
|
| 87# Match the memories with the CPUs, the driver system always simple,
88# and based on the options for the test system
89DriveMemClass = SimpleMemory
90TestMemClass = Simulation.setMemClass(options)
91
|
87if options.benchmark:
88 try:
89 bm = Benchmarks[options.benchmark]
90 except KeyError:
91 print "Error benchmark %s has not been defined." % options.benchmark
92 print "Valid benchmarks are: %s" % DefinedBenchmarks
93 sys.exit(1)
94else:
95 if options.dual:
96 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
97 else:
98 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
99
100np = options.num_cpus
101
102if buildEnv['TARGET_ISA'] == "alpha":
| 92if options.benchmark:
93 try:
94 bm = Benchmarks[options.benchmark]
95 except KeyError:
96 print "Error benchmark %s has not been defined." % options.benchmark
97 print "Valid benchmarks are: %s" % DefinedBenchmarks
98 sys.exit(1)
99else:
100 if options.dual:
101 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
102 else:
103 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
104
105np = options.num_cpus
106
107if buildEnv['TARGET_ISA'] == "alpha":
|
103 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
| 108 test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0])
|
104elif buildEnv['TARGET_ISA'] == "mips":
| 109elif buildEnv['TARGET_ISA'] == "mips":
|
105 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
| 110 test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0])
|
106elif buildEnv['TARGET_ISA'] == "sparc":
| 111elif buildEnv['TARGET_ISA'] == "sparc":
|
107 test_sys = makeSparcSystem(test_mem_mode, bm[0])
| 112 test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0])
|
108elif buildEnv['TARGET_ISA'] == "x86":
| 113elif buildEnv['TARGET_ISA'] == "x86":
|
109 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
| 114 test_sys = makeLinuxX86System(test_mem_mode, TestMemClass,
115 options.num_cpus, bm[0])
|
110elif buildEnv['TARGET_ISA'] == "arm":
| 116elif buildEnv['TARGET_ISA'] == "arm":
|
111 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
112 options.dtb_filename, bare_metal=options.bare_metal)
| 117 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
118 TestMemClass, bm[0], options.dtb_filename,
119 bare_metal=options.bare_metal)
|
113else:
114 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
115
116if options.kernel is not None:
117 test_sys.kernel = binary(options.kernel)
118
119if options.script is not None:
120 test_sys.readfile = options.script
121
122test_sys.init_param = options.init_param
123
124test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
125
126if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
127 test_sys.vm = KvmVM()
128
129if options.caches or options.l2cache:
130 test_sys.iocache = IOCache(clock = '1GHz',
131 addr_ranges = test_sys.mem_ranges)
132 test_sys.iocache.cpu_side = test_sys.iobus.master
133 test_sys.iocache.mem_side = test_sys.membus.slave
134else:
135 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
136 test_sys.iobridge.slave = test_sys.iobus.master
137 test_sys.iobridge.master = test_sys.membus.slave
138
139# Sanity check
140if options.fastmem:
141 if TestCPUClass != AtomicSimpleCPU:
142 fatal("Fastmem can only be used with atomic CPU!")
143 if (options.caches or options.l2cache):
144 fatal("You cannot use fastmem in combination with caches!")
145
146for i in xrange(np):
147 if options.fastmem:
148 test_sys.cpu[i].fastmem = True
149 if options.checker:
150 test_sys.cpu[i].addCheckerCpu()
151 test_sys.cpu[i].createThreads()
152
153CacheConfig.config_cache(options, test_sys)
154
155if len(bm) == 2:
156 if buildEnv['TARGET_ISA'] == 'alpha':
| 120else:
121 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
122
123if options.kernel is not None:
124 test_sys.kernel = binary(options.kernel)
125
126if options.script is not None:
127 test_sys.readfile = options.script
128
129test_sys.init_param = options.init_param
130
131test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
132
133if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
134 test_sys.vm = KvmVM()
135
136if options.caches or options.l2cache:
137 test_sys.iocache = IOCache(clock = '1GHz',
138 addr_ranges = test_sys.mem_ranges)
139 test_sys.iocache.cpu_side = test_sys.iobus.master
140 test_sys.iocache.mem_side = test_sys.membus.slave
141else:
142 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
143 test_sys.iobridge.slave = test_sys.iobus.master
144 test_sys.iobridge.master = test_sys.membus.slave
145
146# Sanity check
147if options.fastmem:
148 if TestCPUClass != AtomicSimpleCPU:
149 fatal("Fastmem can only be used with atomic CPU!")
150 if (options.caches or options.l2cache):
151 fatal("You cannot use fastmem in combination with caches!")
152
153for i in xrange(np):
154 if options.fastmem:
155 test_sys.cpu[i].fastmem = True
156 if options.checker:
157 test_sys.cpu[i].addCheckerCpu()
158 test_sys.cpu[i].createThreads()
159
160CacheConfig.config_cache(options, test_sys)
161
162if len(bm) == 2:
163 if buildEnv['TARGET_ISA'] == 'alpha':
|
157 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
| 164 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, bm[1])
|
158 elif buildEnv['TARGET_ISA'] == 'mips':
| 165 elif buildEnv['TARGET_ISA'] == 'mips':
|
159 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
| 166 drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, bm[1])
|
160 elif buildEnv['TARGET_ISA'] == 'sparc':
| 167 elif buildEnv['TARGET_ISA'] == 'sparc':
|
161 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
| 168 drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1])
|
162 elif buildEnv['TARGET_ISA'] == 'x86':
| 169 elif buildEnv['TARGET_ISA'] == 'x86':
|
163 drive_sys = makeX86System(drive_mem_mode, np, bm[1])
| 170 drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1])
|
164 elif buildEnv['TARGET_ISA'] == 'arm':
| 171 elif buildEnv['TARGET_ISA'] == 'arm':
|
165 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
| 172 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
173 DriveMemClass, bm[1])
|
166
167 drive_sys.cpu = DriveCPUClass(cpu_id=0)
168 drive_sys.cpu.createThreads()
169 drive_sys.cpu.createInterruptController()
170 drive_sys.cpu.connectAllPorts(drive_sys.membus)
171 if options.fastmem:
172 drive_sys.cpu.fastmem = True
173 if options.kernel is not None:
174 drive_sys.kernel = binary(options.kernel)
175
176 if is_kvm_cpu(DriveCPUClass):
177 drive_sys.vm = KvmVM()
178
179 drive_sys.iobridge = Bridge(delay='50ns',
180 ranges = drive_sys.mem_ranges)
181 drive_sys.iobridge.slave = drive_sys.iobus.master
182 drive_sys.iobridge.master = drive_sys.membus.slave
183
184 drive_sys.init_param = options.init_param
185 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
186elif len(bm) == 1:
187 root = Root(full_system=True, system=test_sys)
188else:
189 print "Error I don't know how to create more than 2 systems."
190 sys.exit(1)
191
192if options.timesync:
193 root.time_sync_enable = True
194
195if options.frame_capture:
196 VncServer.frame_capture = True
197
198Simulation.setWorkCountOptions(test_sys, options)
199Simulation.run(options, root, test_sys, FutureClass)
| 174
175 drive_sys.cpu = DriveCPUClass(cpu_id=0)
176 drive_sys.cpu.createThreads()
177 drive_sys.cpu.createInterruptController()
178 drive_sys.cpu.connectAllPorts(drive_sys.membus)
179 if options.fastmem:
180 drive_sys.cpu.fastmem = True
181 if options.kernel is not None:
182 drive_sys.kernel = binary(options.kernel)
183
184 if is_kvm_cpu(DriveCPUClass):
185 drive_sys.vm = KvmVM()
186
187 drive_sys.iobridge = Bridge(delay='50ns',
188 ranges = drive_sys.mem_ranges)
189 drive_sys.iobridge.slave = drive_sys.iobus.master
190 drive_sys.iobridge.master = drive_sys.membus.slave
191
192 drive_sys.init_param = options.init_param
193 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
194elif len(bm) == 1:
195 root = Root(full_system=True, system=test_sys)
196else:
197 print "Error I don't know how to create more than 2 systems."
198 sys.exit(1)
199
200if options.timesync:
201 root.time_sync_enable = True
202
203if options.frame_capture:
204 VncServer.frame_capture = True
205
206Simulation.setWorkCountOptions(test_sys, options)
207Simulation.run(options, root, test_sys, FutureClass)
|