1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40
41import optparse
42import sys
43
44import m5
45from m5.defines import buildEnv
46from m5.objects import *
47from m5.util import addToPath, fatal
48
49addToPath('../common')
50
51from FSConfig import *
52from SysPaths import *
53from Benchmarks import *
54import Simulation
55import CacheConfig
56from Caches import *
57import Options
58
59parser = optparse.OptionParser()
60Options.addCommonOptions(parser)
61Options.addFSOptions(parser)
62
63(options, args) = parser.parse_args()
64
65if args:
66 print "Error: script doesn't take any positional arguments"
67 sys.exit(1)
68
69# driver system CPU is always simple... note this is an assignment of
70# a class, not an instance.
71DriveCPUClass = AtomicSimpleCPU
72drive_mem_mode = 'atomic'
73
74# system under test can be any CPU
75(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
76
77TestCPUClass.clock = '2GHz'
78DriveCPUClass.clock = '2GHz'
79
80if options.benchmark:
81 try:
82 bm = Benchmarks[options.benchmark]
83 except KeyError:
84 print "Error benchmark %s has not been defined." % options.benchmark
85 print "Valid benchmarks are: %s" % DefinedBenchmarks
86 sys.exit(1)
87else:
88 if options.dual:
89 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
90 else:
91 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
92
93np = options.num_cpus
94
95if buildEnv['TARGET_ISA'] == "alpha":
96 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
97elif buildEnv['TARGET_ISA'] == "mips":
98 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
99elif buildEnv['TARGET_ISA'] == "sparc":
100 test_sys = makeSparcSystem(test_mem_mode, bm[0])
101elif buildEnv['TARGET_ISA'] == "x86":
102 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
| 1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40
41import optparse
42import sys
43
44import m5
45from m5.defines import buildEnv
46from m5.objects import *
47from m5.util import addToPath, fatal
48
49addToPath('../common')
50
51from FSConfig import *
52from SysPaths import *
53from Benchmarks import *
54import Simulation
55import CacheConfig
56from Caches import *
57import Options
58
59parser = optparse.OptionParser()
60Options.addCommonOptions(parser)
61Options.addFSOptions(parser)
62
63(options, args) = parser.parse_args()
64
65if args:
66 print "Error: script doesn't take any positional arguments"
67 sys.exit(1)
68
69# driver system CPU is always simple... note this is an assignment of
70# a class, not an instance.
71DriveCPUClass = AtomicSimpleCPU
72drive_mem_mode = 'atomic'
73
74# system under test can be any CPU
75(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
76
77TestCPUClass.clock = '2GHz'
78DriveCPUClass.clock = '2GHz'
79
80if options.benchmark:
81 try:
82 bm = Benchmarks[options.benchmark]
83 except KeyError:
84 print "Error benchmark %s has not been defined." % options.benchmark
85 print "Valid benchmarks are: %s" % DefinedBenchmarks
86 sys.exit(1)
87else:
88 if options.dual:
89 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
90 else:
91 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
92
93np = options.num_cpus
94
95if buildEnv['TARGET_ISA'] == "alpha":
96 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
97elif buildEnv['TARGET_ISA'] == "mips":
98 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
99elif buildEnv['TARGET_ISA'] == "sparc":
100 test_sys = makeSparcSystem(test_mem_mode, bm[0])
101elif buildEnv['TARGET_ISA'] == "x86":
102 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
|
109else:
110 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
111
112if options.kernel is not None:
113 test_sys.kernel = binary(options.kernel)
114
115if options.script is not None:
116 test_sys.readfile = options.script
117
118test_sys.init_param = options.init_param
119
120test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
121
122if bm[0]:
123 mem_size = bm[0].mem()
124else:
125 mem_size = SysConfig().mem()
126if options.caches or options.l2cache:
127 test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range])
128 test_sys.iocache.cpu_side = test_sys.iobus.master
129 test_sys.iocache.mem_side = test_sys.membus.slave
130else:
131 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
132 ranges = [test_sys.physmem.range])
133 test_sys.iobridge.slave = test_sys.iobus.master
134 test_sys.iobridge.master = test_sys.membus.slave
135
136# Sanity check
137if options.fastmem and (options.caches or options.l2cache):
138 fatal("You cannot use fastmem in combination with caches!")
139
140for i in xrange(np):
141 if options.fastmem:
142 test_sys.cpu[i].fastmem = True
143 if options.checker:
144 test_sys.cpu[i].addCheckerCpu()
145
146CacheConfig.config_cache(options, test_sys)
147
148if len(bm) == 2:
149 if buildEnv['TARGET_ISA'] == 'alpha':
150 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
151 elif buildEnv['TARGET_ISA'] == 'mips':
152 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
153 elif buildEnv['TARGET_ISA'] == 'sparc':
154 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
155 elif buildEnv['TARGET_ISA'] == 'x86':
156 drive_sys = makeX86System(drive_mem_mode, np, bm[1])
157 elif buildEnv['TARGET_ISA'] == 'arm':
158 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
159
160 drive_sys.cpu = DriveCPUClass(cpu_id=0)
161 drive_sys.cpu.createInterruptController()
162 drive_sys.cpu.connectAllPorts(drive_sys.membus)
163 if options.fastmem:
164 drive_sys.cpu.fastmem = True
165 if options.kernel is not None:
166 drive_sys.kernel = binary(options.kernel)
167 drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
168 ranges = [drive_sys.physmem.range])
169 drive_sys.iobridge.slave = drive_sys.iobus.master
170 drive_sys.iobridge.master = drive_sys.membus.slave
171
172 drive_sys.init_param = options.init_param
173 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
174elif len(bm) == 1:
175 root = Root(full_system=True, system=test_sys)
176else:
177 print "Error I don't know how to create more than 2 systems."
178 sys.exit(1)
179
180if options.timesync:
181 root.time_sync_enable = True
182
183if options.frame_capture:
184 VncServer.frame_capture = True
185
| 107else:
108 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
109
110if options.kernel is not None:
111 test_sys.kernel = binary(options.kernel)
112
113if options.script is not None:
114 test_sys.readfile = options.script
115
116test_sys.init_param = options.init_param
117
118test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
119
120if bm[0]:
121 mem_size = bm[0].mem()
122else:
123 mem_size = SysConfig().mem()
124if options.caches or options.l2cache:
125 test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range])
126 test_sys.iocache.cpu_side = test_sys.iobus.master
127 test_sys.iocache.mem_side = test_sys.membus.slave
128else:
129 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
130 ranges = [test_sys.physmem.range])
131 test_sys.iobridge.slave = test_sys.iobus.master
132 test_sys.iobridge.master = test_sys.membus.slave
133
134# Sanity check
135if options.fastmem and (options.caches or options.l2cache):
136 fatal("You cannot use fastmem in combination with caches!")
137
138for i in xrange(np):
139 if options.fastmem:
140 test_sys.cpu[i].fastmem = True
141 if options.checker:
142 test_sys.cpu[i].addCheckerCpu()
143
144CacheConfig.config_cache(options, test_sys)
145
146if len(bm) == 2:
147 if buildEnv['TARGET_ISA'] == 'alpha':
148 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
149 elif buildEnv['TARGET_ISA'] == 'mips':
150 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
151 elif buildEnv['TARGET_ISA'] == 'sparc':
152 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
153 elif buildEnv['TARGET_ISA'] == 'x86':
154 drive_sys = makeX86System(drive_mem_mode, np, bm[1])
155 elif buildEnv['TARGET_ISA'] == 'arm':
156 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
157
158 drive_sys.cpu = DriveCPUClass(cpu_id=0)
159 drive_sys.cpu.createInterruptController()
160 drive_sys.cpu.connectAllPorts(drive_sys.membus)
161 if options.fastmem:
162 drive_sys.cpu.fastmem = True
163 if options.kernel is not None:
164 drive_sys.kernel = binary(options.kernel)
165 drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns',
166 ranges = [drive_sys.physmem.range])
167 drive_sys.iobridge.slave = drive_sys.iobus.master
168 drive_sys.iobridge.master = drive_sys.membus.slave
169
170 drive_sys.init_param = options.init_param
171 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
172elif len(bm) == 1:
173 root = Root(full_system=True, system=test_sys)
174else:
175 print "Error I don't know how to create more than 2 systems."
176 sys.exit(1)
177
178if options.timesync:
179 root.time_sync_enable = True
180
181if options.frame_capture:
182 VncServer.frame_capture = True
183
|