1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40
41import optparse
42import os
43import sys
44
45import m5
46from m5.defines import buildEnv
47from m5.objects import *
48from m5.util import addToPath, fatal
49
50if not buildEnv['FULL_SYSTEM']:
51 fatal("This script requires full-system mode (*_FS).")
52
53addToPath('../common')
54
55from FSConfig import *
56from SysPaths import *
57from Benchmarks import *
58import Simulation
59import CacheConfig
60from Caches import *
61
62# Get paths we might need. It's expected this file is in m5/configs/example.
63config_path = os.path.dirname(os.path.abspath(__file__))
64config_root = os.path.dirname(config_path)
65
66parser = optparse.OptionParser()
67
68# Simulation options
69parser.add_option("--timesync", action="store_true",
70 help="Prevent simulated time from getting ahead of real time")
71
72# System options
73parser.add_option("--kernel", action="store", type="string")
74parser.add_option("--script", action="store", type="string")
75if buildEnv['TARGET_ISA'] == "arm":
76 parser.add_option("--bare-metal", action="store_true",
77 help="Provide the raw system without the linux specific bits")
78 parser.add_option("--machine-type", action="store", type="choice",
79 choices=ArmMachineType.map.keys(), default="RealView_PBX")
80# Benchmark options
81parser.add_option("--dual", action="store_true",
82 help="Simulate two systems attached with an ethernet link")
83parser.add_option("-b", "--benchmark", action="store", type="string",
84 dest="benchmark",
85 help="Specify the benchmark to run. Available benchmarks: %s"\
86 % DefinedBenchmarks)
87
88# Metafile options
89parser.add_option("--etherdump", action="store", type="string", dest="etherdump",
90 help="Specify the filename to dump a pcap capture of the" \
91 "ethernet traffic")
92
93execfile(os.path.join(config_root, "common", "Options.py"))
94
95(options, args) = parser.parse_args()
96
97if args:
98 print "Error: script doesn't take any positional arguments"
99 sys.exit(1)
100
101# driver system CPU is always simple... note this is an assignment of
102# a class, not an instance.
103DriveCPUClass = AtomicSimpleCPU
104drive_mem_mode = 'atomic'
105
106# system under test can be any CPU
107(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
108
109TestCPUClass.clock = '2GHz'
110DriveCPUClass.clock = '2GHz'
111
112if options.benchmark:
113 try:
114 bm = Benchmarks[options.benchmark]
115 except KeyError:
116 print "Error benchmark %s has not been defined." % options.benchmark
117 print "Valid benchmarks are: %s" % DefinedBenchmarks
118 sys.exit(1)
119else:
120 if options.dual:
121 bm = [SysConfig(), SysConfig()]
122 else:
123 bm = [SysConfig()]
124
125np = options.num_cpus
126
127if buildEnv['TARGET_ISA'] == "alpha":
128 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
129elif buildEnv['TARGET_ISA'] == "mips":
130 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
131elif buildEnv['TARGET_ISA'] == "sparc":
132 test_sys = makeSparcSystem(test_mem_mode, bm[0])
133elif buildEnv['TARGET_ISA'] == "x86":
134 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
135 setWorkCountOptions(test_sys, options)
136elif buildEnv['TARGET_ISA'] == "arm":
137 test_sys = makeArmSystem(test_mem_mode,
138 options.machine_type, bm[0],
139 bare_metal=options.bare_metal)
| 1# Copyright (c) 2010 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40
41import optparse
42import os
43import sys
44
45import m5
46from m5.defines import buildEnv
47from m5.objects import *
48from m5.util import addToPath, fatal
49
50if not buildEnv['FULL_SYSTEM']:
51 fatal("This script requires full-system mode (*_FS).")
52
53addToPath('../common')
54
55from FSConfig import *
56from SysPaths import *
57from Benchmarks import *
58import Simulation
59import CacheConfig
60from Caches import *
61
62# Get paths we might need. It's expected this file is in m5/configs/example.
63config_path = os.path.dirname(os.path.abspath(__file__))
64config_root = os.path.dirname(config_path)
65
66parser = optparse.OptionParser()
67
68# Simulation options
69parser.add_option("--timesync", action="store_true",
70 help="Prevent simulated time from getting ahead of real time")
71
72# System options
73parser.add_option("--kernel", action="store", type="string")
74parser.add_option("--script", action="store", type="string")
75if buildEnv['TARGET_ISA'] == "arm":
76 parser.add_option("--bare-metal", action="store_true",
77 help="Provide the raw system without the linux specific bits")
78 parser.add_option("--machine-type", action="store", type="choice",
79 choices=ArmMachineType.map.keys(), default="RealView_PBX")
80# Benchmark options
81parser.add_option("--dual", action="store_true",
82 help="Simulate two systems attached with an ethernet link")
83parser.add_option("-b", "--benchmark", action="store", type="string",
84 dest="benchmark",
85 help="Specify the benchmark to run. Available benchmarks: %s"\
86 % DefinedBenchmarks)
87
88# Metafile options
89parser.add_option("--etherdump", action="store", type="string", dest="etherdump",
90 help="Specify the filename to dump a pcap capture of the" \
91 "ethernet traffic")
92
93execfile(os.path.join(config_root, "common", "Options.py"))
94
95(options, args) = parser.parse_args()
96
97if args:
98 print "Error: script doesn't take any positional arguments"
99 sys.exit(1)
100
101# driver system CPU is always simple... note this is an assignment of
102# a class, not an instance.
103DriveCPUClass = AtomicSimpleCPU
104drive_mem_mode = 'atomic'
105
106# system under test can be any CPU
107(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
108
109TestCPUClass.clock = '2GHz'
110DriveCPUClass.clock = '2GHz'
111
112if options.benchmark:
113 try:
114 bm = Benchmarks[options.benchmark]
115 except KeyError:
116 print "Error benchmark %s has not been defined." % options.benchmark
117 print "Valid benchmarks are: %s" % DefinedBenchmarks
118 sys.exit(1)
119else:
120 if options.dual:
121 bm = [SysConfig(), SysConfig()]
122 else:
123 bm = [SysConfig()]
124
125np = options.num_cpus
126
127if buildEnv['TARGET_ISA'] == "alpha":
128 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
129elif buildEnv['TARGET_ISA'] == "mips":
130 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
131elif buildEnv['TARGET_ISA'] == "sparc":
132 test_sys = makeSparcSystem(test_mem_mode, bm[0])
133elif buildEnv['TARGET_ISA'] == "x86":
134 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
135 setWorkCountOptions(test_sys, options)
136elif buildEnv['TARGET_ISA'] == "arm":
137 test_sys = makeArmSystem(test_mem_mode,
138 options.machine_type, bm[0],
139 bare_metal=options.bare_metal)
|
140else:
141 fatal("incapable of building non-alpha or non-sparc full system!")
142
143if options.kernel is not None:
144 test_sys.kernel = binary(options.kernel)
145
146if options.script is not None:
147 test_sys.readfile = options.script
148
149test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
150
151CacheConfig.config_cache(options, test_sys)
152
153if options.caches or options.l2cache:
154 if bm[0]:
155 mem_size = bm[0].mem()
156 else:
157 mem_size = SysConfig().mem()
158 # For x86, we need to poke a hole for interrupt messages to get back to the
159 # CPU. These use a portion of the physical address space which has a
160 # non-zero prefix in the top nibble. Normal memory accesses have a 0
161 # prefix.
162 if buildEnv['TARGET_ISA'] == 'x86':
163 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)]
164 else:
165 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
166 test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)]
167 test_sys.iocache = IOCache(addr_range=mem_size)
168 test_sys.iocache.cpu_side = test_sys.iobus.port
169 test_sys.iocache.mem_side = test_sys.membus.port
170
171for i in xrange(np):
172 if options.fastmem:
173 test_sys.cpu[i].physmem_port = test_sys.physmem.port
174
175if buildEnv['TARGET_ISA'] == 'mips':
176 setMipsOptions(TestCPUClass)
177
178if len(bm) == 2:
179 if buildEnv['TARGET_ISA'] == 'alpha':
180 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
181 elif buildEnv['TARGET_ISA'] == 'mips':
182 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
183 elif buildEnv['TARGET_ISA'] == 'sparc':
184 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
185 elif buildEnv['TARGET_ISA'] == 'x86':
186 drive_sys = makeX86System(drive_mem_mode, np, bm[1])
187 elif buildEnv['TARGET_ISA'] == 'arm':
188 drive_sys = makeArmSystem(drive_mem_mode,
189 machine_options.machine_type, bm[1])
190 drive_sys.cpu = DriveCPUClass(cpu_id=0)
191 drive_sys.cpu.connectAllPorts(drive_sys.membus)
192 if options.fastmem:
193 drive_sys.cpu.physmem_port = drive_sys.physmem.port
194 if options.kernel is not None:
195 drive_sys.kernel = binary(options.kernel)
196
197 root = makeDualRoot(test_sys, drive_sys, options.etherdump)
198elif len(bm) == 1:
199 root = Root(system=test_sys)
200else:
201 print "Error I don't know how to create more than 2 systems."
202 sys.exit(1)
203
204if options.timesync:
205 root.time_sync_enable = True
206
207Simulation.run(options, root, test_sys, FutureClass)
| 141else:
142 fatal("incapable of building non-alpha or non-sparc full system!")
143
144if options.kernel is not None:
145 test_sys.kernel = binary(options.kernel)
146
147if options.script is not None:
148 test_sys.readfile = options.script
149
150test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
151
152CacheConfig.config_cache(options, test_sys)
153
154if options.caches or options.l2cache:
155 if bm[0]:
156 mem_size = bm[0].mem()
157 else:
158 mem_size = SysConfig().mem()
159 # For x86, we need to poke a hole for interrupt messages to get back to the
160 # CPU. These use a portion of the physical address space which has a
161 # non-zero prefix in the top nibble. Normal memory accesses have a 0
162 # prefix.
163 if buildEnv['TARGET_ISA'] == 'x86':
164 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max >> 4)]
165 else:
166 test_sys.bridge.filter_ranges_a=[AddrRange(0, Addr.max)]
167 test_sys.bridge.filter_ranges_b=[AddrRange(mem_size)]
168 test_sys.iocache = IOCache(addr_range=mem_size)
169 test_sys.iocache.cpu_side = test_sys.iobus.port
170 test_sys.iocache.mem_side = test_sys.membus.port
171
172for i in xrange(np):
173 if options.fastmem:
174 test_sys.cpu[i].physmem_port = test_sys.physmem.port
175
176if buildEnv['TARGET_ISA'] == 'mips':
177 setMipsOptions(TestCPUClass)
178
179if len(bm) == 2:
180 if buildEnv['TARGET_ISA'] == 'alpha':
181 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
182 elif buildEnv['TARGET_ISA'] == 'mips':
183 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
184 elif buildEnv['TARGET_ISA'] == 'sparc':
185 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
186 elif buildEnv['TARGET_ISA'] == 'x86':
187 drive_sys = makeX86System(drive_mem_mode, np, bm[1])
188 elif buildEnv['TARGET_ISA'] == 'arm':
189 drive_sys = makeArmSystem(drive_mem_mode,
190 machine_options.machine_type, bm[1])
191 drive_sys.cpu = DriveCPUClass(cpu_id=0)
192 drive_sys.cpu.connectAllPorts(drive_sys.membus)
193 if options.fastmem:
194 drive_sys.cpu.physmem_port = drive_sys.physmem.port
195 if options.kernel is not None:
196 drive_sys.kernel = binary(options.kernel)
197
198 root = makeDualRoot(test_sys, drive_sys, options.etherdump)
199elif len(bm) == 1:
200 root = Root(system=test_sys)
201else:
202 print "Error I don't know how to create more than 2 systems."
203 sys.exit(1)
204
205if options.timesync:
206 root.time_sync_enable = True
207
208Simulation.run(options, root, test_sys, FutureClass)
|