1# Copyright (c) 2010-2013, 2016, 2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42# Brad Beckmann
43
44from __future__ import print_function
45from __future__ import absolute_import
46
47import optparse
48import sys
49
50import m5
51from m5.defines import buildEnv
52from m5.objects import *
53from m5.util import addToPath, fatal, warn
54from m5.util.fdthelper import *
55
56addToPath('../')
57
58from ruby import Ruby
59
60from common.FSConfig import *
61from common.SysPaths import *
62from common.Benchmarks import *
63from common import Simulation
64from common import CacheConfig
65from common import MemConfig
66from common import CpuConfig
67from common import BPConfig
68from common.Caches import *
69from common import Options
70
71def cmd_line_template():
72 if options.command_line and options.command_line_file:
73 print("Error: --command-line and --command-line-file are "
74 "mutually exclusive")
75 sys.exit(1)
76 if options.command_line:
77 return options.command_line
78 if options.command_line_file:
79 return open(options.command_line_file).read().strip()
80 return None
81
82def build_test_system(np):
83 cmdline = cmd_line_template()
84 if buildEnv['TARGET_ISA'] == "alpha":
85 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
86 cmdline=cmdline)
87 elif buildEnv['TARGET_ISA'] == "mips":
88 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
89 elif buildEnv['TARGET_ISA'] == "sparc":
90 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
91 elif buildEnv['TARGET_ISA'] == "x86":
92 test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby,
93 cmdline=cmdline)
94 elif buildEnv['TARGET_ISA'] == "arm":
95 test_sys = makeArmSystem(test_mem_mode, options.machine_type, np,
96 bm[0], options.dtb_filename,
97 bare_metal=options.bare_metal,
98 cmdline=cmdline,
99 external_memory=
100 options.external_memory_system,
101 ruby=options.ruby,
102 security=options.enable_security_extensions)
103 if options.enable_context_switch_stats_dump:
104 test_sys.enable_context_switch_stats_dump = True
105 else:
106 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
107
108 # Set the cache line size for the entire system
109 test_sys.cache_line_size = options.cacheline_size
110
111 # Create a top-level voltage domain
112 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
113
114 # Create a source clock for the system and set the clock period
115 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
116 voltage_domain = test_sys.voltage_domain)
117
118 # Create a CPU voltage domain
119 test_sys.cpu_voltage_domain = VoltageDomain()
120
121 # Create a source clock for the CPUs and set the clock period
122 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
123 voltage_domain =
124 test_sys.cpu_voltage_domain)
125
126 if options.kernel is not None:
127 test_sys.kernel = binary(options.kernel)
128 else:
129 print("Error: a kernel must be provided to run in full system mode")
130 sys.exit(1)
131
132 if options.script is not None:
133 test_sys.readfile = options.script
134
135 if options.lpae:
136 test_sys.have_lpae = True
137
138 if options.virtualisation:
139 test_sys.have_virtualization = True
140
141 test_sys.init_param = options.init_param
142
143 # For now, assign all the CPUs to the same clock domain
144 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
145 for i in range(np)]
146
147 if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass):
148 test_sys.kvm_vm = KvmVM()
149
150 if options.ruby:
151 bootmem = getattr(test_sys, 'bootmem', None)
152 Ruby.create_system(options, True, test_sys, test_sys.iobus,
153 test_sys._dma_ports, bootmem)
154
155 # Create a seperate clock domain for Ruby
156 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
157 voltage_domain = test_sys.voltage_domain)
158
159 # Connect the ruby io port to the PIO bus,
160 # assuming that there is just one such port.
161 test_sys.iobus.master = test_sys.ruby._io_port.slave
162
163 for (i, cpu) in enumerate(test_sys.cpu):
164 #
165 # Tie the cpu ports to the correct ruby system ports
166 #
167 cpu.clk_domain = test_sys.cpu_clk_domain
168 cpu.createThreads()
169 cpu.createInterruptController()
170
171 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
172 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
173
174 if buildEnv['TARGET_ISA'] in ("x86", "arm"):
175 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
176 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
177
178 if buildEnv['TARGET_ISA'] in "x86":
179 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
180 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
181 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
182
183 else:
184 if options.caches or options.l2cache:
185 # By default the IOCache runs at the system clock
186 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
187 test_sys.iocache.cpu_side = test_sys.iobus.master
188 test_sys.iocache.mem_side = test_sys.membus.slave
189 elif not options.external_memory_system:
190 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
191 test_sys.iobridge.slave = test_sys.iobus.master
192 test_sys.iobridge.master = test_sys.membus.slave
193
194 # Sanity check
195 if options.simpoint_profile:
196 if not CpuConfig.is_noncaching_cpu(TestCPUClass):
197 fatal("SimPoint generation should be done with atomic cpu")
198 if np > 1:
199 fatal("SimPoint generation not supported with more than one CPUs")
200
201 for i in range(np):
202 if options.simpoint_profile:
203 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
204 if options.checker:
205 test_sys.cpu[i].addCheckerCpu()
206 if options.bp_type:
207 bpClass = BPConfig.get(options.bp_type)
208 test_sys.cpu[i].branchPred = bpClass()
| 1# Copyright (c) 2010-2013, 2016, 2019 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42# Brad Beckmann
43
44from __future__ import print_function
45from __future__ import absolute_import
46
47import optparse
48import sys
49
50import m5
51from m5.defines import buildEnv
52from m5.objects import *
53from m5.util import addToPath, fatal, warn
54from m5.util.fdthelper import *
55
56addToPath('../')
57
58from ruby import Ruby
59
60from common.FSConfig import *
61from common.SysPaths import *
62from common.Benchmarks import *
63from common import Simulation
64from common import CacheConfig
65from common import MemConfig
66from common import CpuConfig
67from common import BPConfig
68from common.Caches import *
69from common import Options
70
71def cmd_line_template():
72 if options.command_line and options.command_line_file:
73 print("Error: --command-line and --command-line-file are "
74 "mutually exclusive")
75 sys.exit(1)
76 if options.command_line:
77 return options.command_line
78 if options.command_line_file:
79 return open(options.command_line_file).read().strip()
80 return None
81
82def build_test_system(np):
83 cmdline = cmd_line_template()
84 if buildEnv['TARGET_ISA'] == "alpha":
85 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
86 cmdline=cmdline)
87 elif buildEnv['TARGET_ISA'] == "mips":
88 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
89 elif buildEnv['TARGET_ISA'] == "sparc":
90 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
91 elif buildEnv['TARGET_ISA'] == "x86":
92 test_sys = makeLinuxX86System(test_mem_mode, np, bm[0], options.ruby,
93 cmdline=cmdline)
94 elif buildEnv['TARGET_ISA'] == "arm":
95 test_sys = makeArmSystem(test_mem_mode, options.machine_type, np,
96 bm[0], options.dtb_filename,
97 bare_metal=options.bare_metal,
98 cmdline=cmdline,
99 external_memory=
100 options.external_memory_system,
101 ruby=options.ruby,
102 security=options.enable_security_extensions)
103 if options.enable_context_switch_stats_dump:
104 test_sys.enable_context_switch_stats_dump = True
105 else:
106 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
107
108 # Set the cache line size for the entire system
109 test_sys.cache_line_size = options.cacheline_size
110
111 # Create a top-level voltage domain
112 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
113
114 # Create a source clock for the system and set the clock period
115 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
116 voltage_domain = test_sys.voltage_domain)
117
118 # Create a CPU voltage domain
119 test_sys.cpu_voltage_domain = VoltageDomain()
120
121 # Create a source clock for the CPUs and set the clock period
122 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
123 voltage_domain =
124 test_sys.cpu_voltage_domain)
125
126 if options.kernel is not None:
127 test_sys.kernel = binary(options.kernel)
128 else:
129 print("Error: a kernel must be provided to run in full system mode")
130 sys.exit(1)
131
132 if options.script is not None:
133 test_sys.readfile = options.script
134
135 if options.lpae:
136 test_sys.have_lpae = True
137
138 if options.virtualisation:
139 test_sys.have_virtualization = True
140
141 test_sys.init_param = options.init_param
142
143 # For now, assign all the CPUs to the same clock domain
144 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
145 for i in range(np)]
146
147 if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass):
148 test_sys.kvm_vm = KvmVM()
149
150 if options.ruby:
151 bootmem = getattr(test_sys, 'bootmem', None)
152 Ruby.create_system(options, True, test_sys, test_sys.iobus,
153 test_sys._dma_ports, bootmem)
154
155 # Create a seperate clock domain for Ruby
156 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
157 voltage_domain = test_sys.voltage_domain)
158
159 # Connect the ruby io port to the PIO bus,
160 # assuming that there is just one such port.
161 test_sys.iobus.master = test_sys.ruby._io_port.slave
162
163 for (i, cpu) in enumerate(test_sys.cpu):
164 #
165 # Tie the cpu ports to the correct ruby system ports
166 #
167 cpu.clk_domain = test_sys.cpu_clk_domain
168 cpu.createThreads()
169 cpu.createInterruptController()
170
171 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
172 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
173
174 if buildEnv['TARGET_ISA'] in ("x86", "arm"):
175 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
176 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
177
178 if buildEnv['TARGET_ISA'] in "x86":
179 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
180 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
181 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
182
183 else:
184 if options.caches or options.l2cache:
185 # By default the IOCache runs at the system clock
186 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
187 test_sys.iocache.cpu_side = test_sys.iobus.master
188 test_sys.iocache.mem_side = test_sys.membus.slave
189 elif not options.external_memory_system:
190 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
191 test_sys.iobridge.slave = test_sys.iobus.master
192 test_sys.iobridge.master = test_sys.membus.slave
193
194 # Sanity check
195 if options.simpoint_profile:
196 if not CpuConfig.is_noncaching_cpu(TestCPUClass):
197 fatal("SimPoint generation should be done with atomic cpu")
198 if np > 1:
199 fatal("SimPoint generation not supported with more than one CPUs")
200
201 for i in range(np):
202 if options.simpoint_profile:
203 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
204 if options.checker:
205 test_sys.cpu[i].addCheckerCpu()
206 if options.bp_type:
207 bpClass = BPConfig.get(options.bp_type)
208 test_sys.cpu[i].branchPred = bpClass()
|
| 209 if options.indirect_bp_type:
210 IndirectBPClass = \
211 BPConfig.get_indirect(options.indirect_bp_type)
212 test_sys.cpu[i].branchPred.indirectBranchPred = \
213 IndirectBPClass()
|
209 test_sys.cpu[i].createThreads()
210
211 # If elastic tracing is enabled when not restoring from checkpoint and
212 # when not fast forwarding using the atomic cpu, then check that the
213 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
214 # passes then attach the elastic trace probe.
215 # If restoring from checkpoint or fast forwarding, the code that does this for
216 # FutureCPUClass is in the Simulation module. If the check passes then the
217 # elastic trace probe is attached to the switch CPUs.
218 if options.elastic_trace_en and options.checkpoint_restore == None and \
219 not options.fast_forward:
220 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
221
222 CacheConfig.config_cache(options, test_sys)
223
224 MemConfig.config_mem(options, test_sys)
225
226 return test_sys
227
228def build_drive_system(np):
229 # driver system CPU is always simple, so is the memory
230 # Note this is an assignment of a class, not an instance.
231 DriveCPUClass = AtomicSimpleCPU
232 drive_mem_mode = 'atomic'
233 DriveMemClass = SimpleMemory
234
235 cmdline = cmd_line_template()
236 if buildEnv['TARGET_ISA'] == 'alpha':
237 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1],
238 cmdline=cmdline)
239 elif buildEnv['TARGET_ISA'] == 'mips':
240 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
241 elif buildEnv['TARGET_ISA'] == 'sparc':
242 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
243 elif buildEnv['TARGET_ISA'] == 'x86':
244 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
245 cmdline=cmdline)
246 elif buildEnv['TARGET_ISA'] == 'arm':
247 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
248 bm[1], options.dtb_filename, cmdline=cmdline)
249
250 # Create a top-level voltage domain
251 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
252
253 # Create a source clock for the system and set the clock period
254 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
255 voltage_domain = drive_sys.voltage_domain)
256
257 # Create a CPU voltage domain
258 drive_sys.cpu_voltage_domain = VoltageDomain()
259
260 # Create a source clock for the CPUs and set the clock period
261 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
262 voltage_domain =
263 drive_sys.cpu_voltage_domain)
264
265 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
266 cpu_id=0)
267 drive_sys.cpu.createThreads()
268 drive_sys.cpu.createInterruptController()
269 drive_sys.cpu.connectAllPorts(drive_sys.membus)
270 if options.kernel is not None:
271 drive_sys.kernel = binary(options.kernel)
272 else:
273 print("Error: a kernel must be provided to run in full system mode")
274 sys.exit(1)
275
276 if CpuConfig.is_kvm_cpu(DriveCPUClass):
277 drive_sys.kvm_vm = KvmVM()
278
279 drive_sys.iobridge = Bridge(delay='50ns',
280 ranges = drive_sys.mem_ranges)
281 drive_sys.iobridge.slave = drive_sys.iobus.master
282 drive_sys.iobridge.master = drive_sys.membus.slave
283
284 # Create the appropriate memory controllers and connect them to the
285 # memory bus
286 drive_sys.mem_ctrls = [DriveMemClass(range = r)
287 for r in drive_sys.mem_ranges]
288 for i in range(len(drive_sys.mem_ctrls)):
289 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
290
291 drive_sys.init_param = options.init_param
292
293 return drive_sys
294
295# Add options
296parser = optparse.OptionParser()
297Options.addCommonOptions(parser)
298Options.addFSOptions(parser)
299
300# Add the ruby specific and protocol specific options
301if '--ruby' in sys.argv:
302 Ruby.define_options(parser)
303
304(options, args) = parser.parse_args()
305
306if args:
307 print("Error: script doesn't take any positional arguments")
308 sys.exit(1)
309
310# system under test can be any CPU
311(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
312
313# Match the memories with the CPUs, based on the options for the test system
314TestMemClass = Simulation.setMemClass(options)
315
316if options.benchmark:
317 try:
318 bm = Benchmarks[options.benchmark]
319 except KeyError:
320 print("Error benchmark %s has not been defined." % options.benchmark)
321 print("Valid benchmarks are: %s" % DefinedBenchmarks)
322 sys.exit(1)
323else:
324 if options.dual:
325 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
326 mem=options.mem_size, os_type=options.os_type),
327 SysConfig(disk=options.disk_image, rootdev=options.root_device,
328 mem=options.mem_size, os_type=options.os_type)]
329 else:
330 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
331 mem=options.mem_size, os_type=options.os_type)]
332
333np = options.num_cpus
334
335test_sys = build_test_system(np)
336if len(bm) == 2:
337 drive_sys = build_drive_system(np)
338 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
339elif len(bm) == 1 and options.dist:
340 # This system is part of a dist-gem5 simulation
341 root = makeDistRoot(test_sys,
342 options.dist_rank,
343 options.dist_size,
344 options.dist_server_name,
345 options.dist_server_port,
346 options.dist_sync_repeat,
347 options.dist_sync_start,
348 options.ethernet_linkspeed,
349 options.ethernet_linkdelay,
350 options.etherdump);
351elif len(bm) == 1:
352 root = Root(full_system=True, system=test_sys)
353else:
354 print("Error I don't know how to create more than 2 systems.")
355 sys.exit(1)
356
357if options.timesync:
358 root.time_sync_enable = True
359
360if options.frame_capture:
361 VncServer.frame_capture = True
362
363if buildEnv['TARGET_ISA'] == "arm" and not options.bare_metal \
364 and not options.dtb_filename:
365 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
366 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
367 "platforms, unless custom hardware models have been equipped "\
368 "with generation functionality.")
369
370 # Generate a Device Tree
371 for sysname in ('system', 'testsys', 'drivesys'):
372 if hasattr(root, sysname):
373 sys = getattr(root, sysname)
374 sys.generateDtb(m5.options.outdir, '%s.dtb' % sysname)
375
376Simulation.setWorkCountOptions(test_sys, options)
377Simulation.run(options, root, test_sys, FutureClass)
| 214 test_sys.cpu[i].createThreads()
215
216 # If elastic tracing is enabled when not restoring from checkpoint and
217 # when not fast forwarding using the atomic cpu, then check that the
218 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
219 # passes then attach the elastic trace probe.
220 # If restoring from checkpoint or fast forwarding, the code that does this for
221 # FutureCPUClass is in the Simulation module. If the check passes then the
222 # elastic trace probe is attached to the switch CPUs.
223 if options.elastic_trace_en and options.checkpoint_restore == None and \
224 not options.fast_forward:
225 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
226
227 CacheConfig.config_cache(options, test_sys)
228
229 MemConfig.config_mem(options, test_sys)
230
231 return test_sys
232
233def build_drive_system(np):
234 # driver system CPU is always simple, so is the memory
235 # Note this is an assignment of a class, not an instance.
236 DriveCPUClass = AtomicSimpleCPU
237 drive_mem_mode = 'atomic'
238 DriveMemClass = SimpleMemory
239
240 cmdline = cmd_line_template()
241 if buildEnv['TARGET_ISA'] == 'alpha':
242 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1],
243 cmdline=cmdline)
244 elif buildEnv['TARGET_ISA'] == 'mips':
245 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
246 elif buildEnv['TARGET_ISA'] == 'sparc':
247 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
248 elif buildEnv['TARGET_ISA'] == 'x86':
249 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
250 cmdline=cmdline)
251 elif buildEnv['TARGET_ISA'] == 'arm':
252 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
253 bm[1], options.dtb_filename, cmdline=cmdline)
254
255 # Create a top-level voltage domain
256 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
257
258 # Create a source clock for the system and set the clock period
259 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
260 voltage_domain = drive_sys.voltage_domain)
261
262 # Create a CPU voltage domain
263 drive_sys.cpu_voltage_domain = VoltageDomain()
264
265 # Create a source clock for the CPUs and set the clock period
266 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
267 voltage_domain =
268 drive_sys.cpu_voltage_domain)
269
270 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
271 cpu_id=0)
272 drive_sys.cpu.createThreads()
273 drive_sys.cpu.createInterruptController()
274 drive_sys.cpu.connectAllPorts(drive_sys.membus)
275 if options.kernel is not None:
276 drive_sys.kernel = binary(options.kernel)
277 else:
278 print("Error: a kernel must be provided to run in full system mode")
279 sys.exit(1)
280
281 if CpuConfig.is_kvm_cpu(DriveCPUClass):
282 drive_sys.kvm_vm = KvmVM()
283
284 drive_sys.iobridge = Bridge(delay='50ns',
285 ranges = drive_sys.mem_ranges)
286 drive_sys.iobridge.slave = drive_sys.iobus.master
287 drive_sys.iobridge.master = drive_sys.membus.slave
288
289 # Create the appropriate memory controllers and connect them to the
290 # memory bus
291 drive_sys.mem_ctrls = [DriveMemClass(range = r)
292 for r in drive_sys.mem_ranges]
293 for i in range(len(drive_sys.mem_ctrls)):
294 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
295
296 drive_sys.init_param = options.init_param
297
298 return drive_sys
299
300# Add options
301parser = optparse.OptionParser()
302Options.addCommonOptions(parser)
303Options.addFSOptions(parser)
304
305# Add the ruby specific and protocol specific options
306if '--ruby' in sys.argv:
307 Ruby.define_options(parser)
308
309(options, args) = parser.parse_args()
310
311if args:
312 print("Error: script doesn't take any positional arguments")
313 sys.exit(1)
314
315# system under test can be any CPU
316(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
317
318# Match the memories with the CPUs, based on the options for the test system
319TestMemClass = Simulation.setMemClass(options)
320
321if options.benchmark:
322 try:
323 bm = Benchmarks[options.benchmark]
324 except KeyError:
325 print("Error benchmark %s has not been defined." % options.benchmark)
326 print("Valid benchmarks are: %s" % DefinedBenchmarks)
327 sys.exit(1)
328else:
329 if options.dual:
330 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
331 mem=options.mem_size, os_type=options.os_type),
332 SysConfig(disk=options.disk_image, rootdev=options.root_device,
333 mem=options.mem_size, os_type=options.os_type)]
334 else:
335 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
336 mem=options.mem_size, os_type=options.os_type)]
337
338np = options.num_cpus
339
340test_sys = build_test_system(np)
341if len(bm) == 2:
342 drive_sys = build_drive_system(np)
343 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
344elif len(bm) == 1 and options.dist:
345 # This system is part of a dist-gem5 simulation
346 root = makeDistRoot(test_sys,
347 options.dist_rank,
348 options.dist_size,
349 options.dist_server_name,
350 options.dist_server_port,
351 options.dist_sync_repeat,
352 options.dist_sync_start,
353 options.ethernet_linkspeed,
354 options.ethernet_linkdelay,
355 options.etherdump);
356elif len(bm) == 1:
357 root = Root(full_system=True, system=test_sys)
358else:
359 print("Error I don't know how to create more than 2 systems.")
360 sys.exit(1)
361
362if options.timesync:
363 root.time_sync_enable = True
364
365if options.frame_capture:
366 VncServer.frame_capture = True
367
368if buildEnv['TARGET_ISA'] == "arm" and not options.bare_metal \
369 and not options.dtb_filename:
370 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
371 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
372 "platforms, unless custom hardware models have been equipped "\
373 "with generation functionality.")
374
375 # Generate a Device Tree
376 for sysname in ('system', 'testsys', 'drivesys'):
377 if hasattr(root, sysname):
378 sys = getattr(root, sysname)
379 sys.generateDtb(m5.options.outdir, '%s.dtb' % sysname)
380
381Simulation.setWorkCountOptions(test_sys, options)
382Simulation.run(options, root, test_sys, FutureClass)
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