1# Copyright (c) 2010-2013, 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42# Brad Beckmann
43
44from __future__ import print_function
45
46import optparse
47import sys
48
49import m5
50from m5.defines import buildEnv
51from m5.objects import *
52from m5.util import addToPath, fatal, warn
53from m5.util.fdthelper import *
54
55addToPath('../')
56
57from ruby import Ruby
58
59from common.FSConfig import *
60from common.SysPaths import *
61from common.Benchmarks import *
62from common import Simulation
63from common import CacheConfig
64from common import MemConfig
65from common import CpuConfig
66from common.Caches import *
67from common import Options
68
69def cmd_line_template():
70 if options.command_line and options.command_line_file:
71 print("Error: --command-line and --command-line-file are "
72 "mutually exclusive")
73 sys.exit(1)
74 if options.command_line:
75 return options.command_line
76 if options.command_line_file:
77 return open(options.command_line_file).read().strip()
78 return None
79
80def build_test_system(np):
81 cmdline = cmd_line_template()
82 if buildEnv['TARGET_ISA'] == "alpha":
83 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
84 cmdline=cmdline)
85 elif buildEnv['TARGET_ISA'] == "mips":
86 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
87 elif buildEnv['TARGET_ISA'] == "sparc":
88 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
89 elif buildEnv['TARGET_ISA'] == "x86":
90 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
91 options.ruby, cmdline=cmdline)
92 elif buildEnv['TARGET_ISA'] == "arm":
93 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
94 options.num_cpus, bm[0], options.dtb_filename,
95 bare_metal=options.bare_metal,
96 cmdline=cmdline,
97 ignore_dtb=options.generate_dtb,
98 external_memory=
99 options.external_memory_system,
100 ruby=options.ruby,
101 security=options.enable_security_extensions)
102 if options.enable_context_switch_stats_dump:
103 test_sys.enable_context_switch_stats_dump = True
104 else:
105 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
106
107 # Set the cache line size for the entire system
108 test_sys.cache_line_size = options.cacheline_size
109
110 # Create a top-level voltage domain
111 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
112
113 # Create a source clock for the system and set the clock period
114 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
115 voltage_domain = test_sys.voltage_domain)
116
117 # Create a CPU voltage domain
118 test_sys.cpu_voltage_domain = VoltageDomain()
119
120 # Create a source clock for the CPUs and set the clock period
121 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
122 voltage_domain =
123 test_sys.cpu_voltage_domain)
124
125 if options.kernel is not None:
126 test_sys.kernel = binary(options.kernel)
127
128 if options.script is not None:
129 test_sys.readfile = options.script
130
131 if options.lpae:
132 test_sys.have_lpae = True
133
134 if options.virtualisation:
135 test_sys.have_virtualization = True
136
137 test_sys.init_param = options.init_param
138
139 # For now, assign all the CPUs to the same clock domain
140 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
141 for i in xrange(np)]
142
143 if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass):
144 test_sys.kvm_vm = KvmVM()
145
146 if options.ruby:
147 bootmem = getattr(test_sys, 'bootmem', None)
148 Ruby.create_system(options, True, test_sys, test_sys.iobus,
149 test_sys._dma_ports, bootmem)
150
151 # Create a seperate clock domain for Ruby
152 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
153 voltage_domain = test_sys.voltage_domain)
154
155 # Connect the ruby io port to the PIO bus,
156 # assuming that there is just one such port.
157 test_sys.iobus.master = test_sys.ruby._io_port.slave
158
159 for (i, cpu) in enumerate(test_sys.cpu):
160 #
161 # Tie the cpu ports to the correct ruby system ports
162 #
163 cpu.clk_domain = test_sys.cpu_clk_domain
164 cpu.createThreads()
165 cpu.createInterruptController()
166
167 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
168 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
169
170 if buildEnv['TARGET_ISA'] in ("x86", "arm"):
171 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
172 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
173
174 if buildEnv['TARGET_ISA'] in "x86":
175 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
176 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
177 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
178
179 else:
180 if options.caches or options.l2cache:
181 # By default the IOCache runs at the system clock
182 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
183 test_sys.iocache.cpu_side = test_sys.iobus.master
184 test_sys.iocache.mem_side = test_sys.membus.slave
185 elif not options.external_memory_system:
186 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
187 test_sys.iobridge.slave = test_sys.iobus.master
188 test_sys.iobridge.master = test_sys.membus.slave
189
190 # Sanity check
| 1# Copyright (c) 2010-2013, 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42# Brad Beckmann
43
44from __future__ import print_function
45
46import optparse
47import sys
48
49import m5
50from m5.defines import buildEnv
51from m5.objects import *
52from m5.util import addToPath, fatal, warn
53from m5.util.fdthelper import *
54
55addToPath('../')
56
57from ruby import Ruby
58
59from common.FSConfig import *
60from common.SysPaths import *
61from common.Benchmarks import *
62from common import Simulation
63from common import CacheConfig
64from common import MemConfig
65from common import CpuConfig
66from common.Caches import *
67from common import Options
68
69def cmd_line_template():
70 if options.command_line and options.command_line_file:
71 print("Error: --command-line and --command-line-file are "
72 "mutually exclusive")
73 sys.exit(1)
74 if options.command_line:
75 return options.command_line
76 if options.command_line_file:
77 return open(options.command_line_file).read().strip()
78 return None
79
80def build_test_system(np):
81 cmdline = cmd_line_template()
82 if buildEnv['TARGET_ISA'] == "alpha":
83 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
84 cmdline=cmdline)
85 elif buildEnv['TARGET_ISA'] == "mips":
86 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
87 elif buildEnv['TARGET_ISA'] == "sparc":
88 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
89 elif buildEnv['TARGET_ISA'] == "x86":
90 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
91 options.ruby, cmdline=cmdline)
92 elif buildEnv['TARGET_ISA'] == "arm":
93 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
94 options.num_cpus, bm[0], options.dtb_filename,
95 bare_metal=options.bare_metal,
96 cmdline=cmdline,
97 ignore_dtb=options.generate_dtb,
98 external_memory=
99 options.external_memory_system,
100 ruby=options.ruby,
101 security=options.enable_security_extensions)
102 if options.enable_context_switch_stats_dump:
103 test_sys.enable_context_switch_stats_dump = True
104 else:
105 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
106
107 # Set the cache line size for the entire system
108 test_sys.cache_line_size = options.cacheline_size
109
110 # Create a top-level voltage domain
111 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
112
113 # Create a source clock for the system and set the clock period
114 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
115 voltage_domain = test_sys.voltage_domain)
116
117 # Create a CPU voltage domain
118 test_sys.cpu_voltage_domain = VoltageDomain()
119
120 # Create a source clock for the CPUs and set the clock period
121 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
122 voltage_domain =
123 test_sys.cpu_voltage_domain)
124
125 if options.kernel is not None:
126 test_sys.kernel = binary(options.kernel)
127
128 if options.script is not None:
129 test_sys.readfile = options.script
130
131 if options.lpae:
132 test_sys.have_lpae = True
133
134 if options.virtualisation:
135 test_sys.have_virtualization = True
136
137 test_sys.init_param = options.init_param
138
139 # For now, assign all the CPUs to the same clock domain
140 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
141 for i in xrange(np)]
142
143 if CpuConfig.is_kvm_cpu(TestCPUClass) or CpuConfig.is_kvm_cpu(FutureClass):
144 test_sys.kvm_vm = KvmVM()
145
146 if options.ruby:
147 bootmem = getattr(test_sys, 'bootmem', None)
148 Ruby.create_system(options, True, test_sys, test_sys.iobus,
149 test_sys._dma_ports, bootmem)
150
151 # Create a seperate clock domain for Ruby
152 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
153 voltage_domain = test_sys.voltage_domain)
154
155 # Connect the ruby io port to the PIO bus,
156 # assuming that there is just one such port.
157 test_sys.iobus.master = test_sys.ruby._io_port.slave
158
159 for (i, cpu) in enumerate(test_sys.cpu):
160 #
161 # Tie the cpu ports to the correct ruby system ports
162 #
163 cpu.clk_domain = test_sys.cpu_clk_domain
164 cpu.createThreads()
165 cpu.createInterruptController()
166
167 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
168 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
169
170 if buildEnv['TARGET_ISA'] in ("x86", "arm"):
171 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
172 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
173
174 if buildEnv['TARGET_ISA'] in "x86":
175 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
176 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
177 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
178
179 else:
180 if options.caches or options.l2cache:
181 # By default the IOCache runs at the system clock
182 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
183 test_sys.iocache.cpu_side = test_sys.iobus.master
184 test_sys.iocache.mem_side = test_sys.membus.slave
185 elif not options.external_memory_system:
186 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
187 test_sys.iobridge.slave = test_sys.iobus.master
188 test_sys.iobridge.master = test_sys.membus.slave
189
190 # Sanity check
|
191 if options.fastmem:
192 if TestCPUClass != AtomicSimpleCPU:
193 fatal("Fastmem can only be used with atomic CPU!")
194 if (options.caches or options.l2cache):
195 fatal("You cannot use fastmem in combination with caches!")
196
| |
197 if options.simpoint_profile:
| 191 if options.simpoint_profile:
|
198 if not options.fastmem:
199 # Atomic CPU checked with fastmem option already
200 fatal("SimPoint generation should be done with atomic cpu and fastmem")
| 192 if not CpuConfig.is_atomic_cpu(TestCPUClass):
193 fatal("SimPoint generation should be done with atomic cpu")
|
201 if np > 1:
202 fatal("SimPoint generation not supported with more than one CPUs")
203
204 for i in xrange(np):
| 194 if np > 1:
195 fatal("SimPoint generation not supported with more than one CPUs")
196
197 for i in xrange(np):
|
205 if options.fastmem:
206 test_sys.cpu[i].fastmem = True
| |
207 if options.simpoint_profile:
208 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
209 if options.checker:
210 test_sys.cpu[i].addCheckerCpu()
211 test_sys.cpu[i].createThreads()
212
213 # If elastic tracing is enabled when not restoring from checkpoint and
214 # when not fast forwarding using the atomic cpu, then check that the
215 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
216 # passes then attach the elastic trace probe.
217 # If restoring from checkpoint or fast forwarding, the code that does this for
218 # FutureCPUClass is in the Simulation module. If the check passes then the
219 # elastic trace probe is attached to the switch CPUs.
220 if options.elastic_trace_en and options.checkpoint_restore == None and \
221 not options.fast_forward:
222 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
223
224 CacheConfig.config_cache(options, test_sys)
225
226 MemConfig.config_mem(options, test_sys)
227
228 return test_sys
229
230def build_drive_system(np):
231 # driver system CPU is always simple, so is the memory
232 # Note this is an assignment of a class, not an instance.
233 DriveCPUClass = AtomicSimpleCPU
234 drive_mem_mode = 'atomic'
235 DriveMemClass = SimpleMemory
236
237 cmdline = cmd_line_template()
238 if buildEnv['TARGET_ISA'] == 'alpha':
239 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline)
240 elif buildEnv['TARGET_ISA'] == 'mips':
241 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
242 elif buildEnv['TARGET_ISA'] == 'sparc':
243 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
244 elif buildEnv['TARGET_ISA'] == 'x86':
245 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
246 cmdline=cmdline)
247 elif buildEnv['TARGET_ISA'] == 'arm':
248 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
249 bm[1], options.dtb_filename, cmdline=cmdline,
250 ignore_dtb=options.generate_dtb)
251
252 # Create a top-level voltage domain
253 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
254
255 # Create a source clock for the system and set the clock period
256 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
257 voltage_domain = drive_sys.voltage_domain)
258
259 # Create a CPU voltage domain
260 drive_sys.cpu_voltage_domain = VoltageDomain()
261
262 # Create a source clock for the CPUs and set the clock period
263 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
264 voltage_domain =
265 drive_sys.cpu_voltage_domain)
266
267 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
268 cpu_id=0)
269 drive_sys.cpu.createThreads()
270 drive_sys.cpu.createInterruptController()
271 drive_sys.cpu.connectAllPorts(drive_sys.membus)
| 198 if options.simpoint_profile:
199 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
200 if options.checker:
201 test_sys.cpu[i].addCheckerCpu()
202 test_sys.cpu[i].createThreads()
203
204 # If elastic tracing is enabled when not restoring from checkpoint and
205 # when not fast forwarding using the atomic cpu, then check that the
206 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
207 # passes then attach the elastic trace probe.
208 # If restoring from checkpoint or fast forwarding, the code that does this for
209 # FutureCPUClass is in the Simulation module. If the check passes then the
210 # elastic trace probe is attached to the switch CPUs.
211 if options.elastic_trace_en and options.checkpoint_restore == None and \
212 not options.fast_forward:
213 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
214
215 CacheConfig.config_cache(options, test_sys)
216
217 MemConfig.config_mem(options, test_sys)
218
219 return test_sys
220
221def build_drive_system(np):
222 # driver system CPU is always simple, so is the memory
223 # Note this is an assignment of a class, not an instance.
224 DriveCPUClass = AtomicSimpleCPU
225 drive_mem_mode = 'atomic'
226 DriveMemClass = SimpleMemory
227
228 cmdline = cmd_line_template()
229 if buildEnv['TARGET_ISA'] == 'alpha':
230 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline)
231 elif buildEnv['TARGET_ISA'] == 'mips':
232 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
233 elif buildEnv['TARGET_ISA'] == 'sparc':
234 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
235 elif buildEnv['TARGET_ISA'] == 'x86':
236 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
237 cmdline=cmdline)
238 elif buildEnv['TARGET_ISA'] == 'arm':
239 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
240 bm[1], options.dtb_filename, cmdline=cmdline,
241 ignore_dtb=options.generate_dtb)
242
243 # Create a top-level voltage domain
244 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
245
246 # Create a source clock for the system and set the clock period
247 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
248 voltage_domain = drive_sys.voltage_domain)
249
250 # Create a CPU voltage domain
251 drive_sys.cpu_voltage_domain = VoltageDomain()
252
253 # Create a source clock for the CPUs and set the clock period
254 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
255 voltage_domain =
256 drive_sys.cpu_voltage_domain)
257
258 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
259 cpu_id=0)
260 drive_sys.cpu.createThreads()
261 drive_sys.cpu.createInterruptController()
262 drive_sys.cpu.connectAllPorts(drive_sys.membus)
|
272 if options.fastmem:
273 drive_sys.cpu.fastmem = True
| |
274 if options.kernel is not None:
275 drive_sys.kernel = binary(options.kernel)
276
277 if CpuConfig.is_kvm_cpu(DriveCPUClass):
278 drive_sys.kvm_vm = KvmVM()
279
280 drive_sys.iobridge = Bridge(delay='50ns',
281 ranges = drive_sys.mem_ranges)
282 drive_sys.iobridge.slave = drive_sys.iobus.master
283 drive_sys.iobridge.master = drive_sys.membus.slave
284
285 # Create the appropriate memory controllers and connect them to the
286 # memory bus
287 drive_sys.mem_ctrls = [DriveMemClass(range = r)
288 for r in drive_sys.mem_ranges]
289 for i in xrange(len(drive_sys.mem_ctrls)):
290 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
291
292 drive_sys.init_param = options.init_param
293
294 return drive_sys
295
296# Add options
297parser = optparse.OptionParser()
298Options.addCommonOptions(parser)
299Options.addFSOptions(parser)
300
301# Add the ruby specific and protocol specific options
302if '--ruby' in sys.argv:
303 Ruby.define_options(parser)
304
305(options, args) = parser.parse_args()
306
307if args:
308 print("Error: script doesn't take any positional arguments")
309 sys.exit(1)
310
311# system under test can be any CPU
312(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
313
314# Match the memories with the CPUs, based on the options for the test system
315TestMemClass = Simulation.setMemClass(options)
316
317if options.benchmark:
318 try:
319 bm = Benchmarks[options.benchmark]
320 except KeyError:
321 print("Error benchmark %s has not been defined." % options.benchmark)
322 print("Valid benchmarks are: %s" % DefinedBenchmarks)
323 sys.exit(1)
324else:
325 if options.dual:
326 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
327 mem=options.mem_size, os_type=options.os_type),
328 SysConfig(disk=options.disk_image, rootdev=options.root_device,
329 mem=options.mem_size, os_type=options.os_type)]
330 else:
331 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
332 mem=options.mem_size, os_type=options.os_type)]
333
334np = options.num_cpus
335
336test_sys = build_test_system(np)
337if len(bm) == 2:
338 drive_sys = build_drive_system(np)
339 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
340elif len(bm) == 1 and options.dist:
341 # This system is part of a dist-gem5 simulation
342 root = makeDistRoot(test_sys,
343 options.dist_rank,
344 options.dist_size,
345 options.dist_server_name,
346 options.dist_server_port,
347 options.dist_sync_repeat,
348 options.dist_sync_start,
349 options.ethernet_linkspeed,
350 options.ethernet_linkdelay,
351 options.etherdump);
352elif len(bm) == 1:
353 root = Root(full_system=True, system=test_sys)
354else:
355 print("Error I don't know how to create more than 2 systems.")
356 sys.exit(1)
357
358if options.timesync:
359 root.time_sync_enable = True
360
361if options.frame_capture:
362 VncServer.frame_capture = True
363
364if buildEnv['TARGET_ISA'] == "arm" and options.generate_dtb:
365 # Sanity checks
366 if options.dtb_filename:
367 fatal("--generate-dtb and --dtb-filename cannot be specified at the"\
368 "same time.")
369
370 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
371 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
372 "platforms, unless custom hardware models have been equipped "\
373 "with generation functionality.")
374
375 # Generate a Device Tree
376 def create_dtb_for_system(system, filename):
377 state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
378 rootNode = system.generateDeviceTree(state)
379
380 fdt = Fdt()
381 fdt.add_rootnode(rootNode)
382 dtb_filename = os.path.join(m5.options.outdir, filename)
383 return fdt.writeDtbFile(dtb_filename)
384
385 for sysname in ('system', 'testsys', 'drivesys'):
386 if hasattr(root, sysname):
387 sys = getattr(root, sysname)
388 sys.dtb_filename = create_dtb_for_system(sys, '%s.dtb' % sysname)
389
390Simulation.setWorkCountOptions(test_sys, options)
391Simulation.run(options, root, test_sys, FutureClass)
| 263 if options.kernel is not None:
264 drive_sys.kernel = binary(options.kernel)
265
266 if CpuConfig.is_kvm_cpu(DriveCPUClass):
267 drive_sys.kvm_vm = KvmVM()
268
269 drive_sys.iobridge = Bridge(delay='50ns',
270 ranges = drive_sys.mem_ranges)
271 drive_sys.iobridge.slave = drive_sys.iobus.master
272 drive_sys.iobridge.master = drive_sys.membus.slave
273
274 # Create the appropriate memory controllers and connect them to the
275 # memory bus
276 drive_sys.mem_ctrls = [DriveMemClass(range = r)
277 for r in drive_sys.mem_ranges]
278 for i in xrange(len(drive_sys.mem_ctrls)):
279 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
280
281 drive_sys.init_param = options.init_param
282
283 return drive_sys
284
285# Add options
286parser = optparse.OptionParser()
287Options.addCommonOptions(parser)
288Options.addFSOptions(parser)
289
290# Add the ruby specific and protocol specific options
291if '--ruby' in sys.argv:
292 Ruby.define_options(parser)
293
294(options, args) = parser.parse_args()
295
296if args:
297 print("Error: script doesn't take any positional arguments")
298 sys.exit(1)
299
300# system under test can be any CPU
301(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
302
303# Match the memories with the CPUs, based on the options for the test system
304TestMemClass = Simulation.setMemClass(options)
305
306if options.benchmark:
307 try:
308 bm = Benchmarks[options.benchmark]
309 except KeyError:
310 print("Error benchmark %s has not been defined." % options.benchmark)
311 print("Valid benchmarks are: %s" % DefinedBenchmarks)
312 sys.exit(1)
313else:
314 if options.dual:
315 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
316 mem=options.mem_size, os_type=options.os_type),
317 SysConfig(disk=options.disk_image, rootdev=options.root_device,
318 mem=options.mem_size, os_type=options.os_type)]
319 else:
320 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
321 mem=options.mem_size, os_type=options.os_type)]
322
323np = options.num_cpus
324
325test_sys = build_test_system(np)
326if len(bm) == 2:
327 drive_sys = build_drive_system(np)
328 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
329elif len(bm) == 1 and options.dist:
330 # This system is part of a dist-gem5 simulation
331 root = makeDistRoot(test_sys,
332 options.dist_rank,
333 options.dist_size,
334 options.dist_server_name,
335 options.dist_server_port,
336 options.dist_sync_repeat,
337 options.dist_sync_start,
338 options.ethernet_linkspeed,
339 options.ethernet_linkdelay,
340 options.etherdump);
341elif len(bm) == 1:
342 root = Root(full_system=True, system=test_sys)
343else:
344 print("Error I don't know how to create more than 2 systems.")
345 sys.exit(1)
346
347if options.timesync:
348 root.time_sync_enable = True
349
350if options.frame_capture:
351 VncServer.frame_capture = True
352
353if buildEnv['TARGET_ISA'] == "arm" and options.generate_dtb:
354 # Sanity checks
355 if options.dtb_filename:
356 fatal("--generate-dtb and --dtb-filename cannot be specified at the"\
357 "same time.")
358
359 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
360 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
361 "platforms, unless custom hardware models have been equipped "\
362 "with generation functionality.")
363
364 # Generate a Device Tree
365 def create_dtb_for_system(system, filename):
366 state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
367 rootNode = system.generateDeviceTree(state)
368
369 fdt = Fdt()
370 fdt.add_rootnode(rootNode)
371 dtb_filename = os.path.join(m5.options.outdir, filename)
372 return fdt.writeDtbFile(dtb_filename)
373
374 for sysname in ('system', 'testsys', 'drivesys'):
375 if hasattr(root, sysname):
376 sys = getattr(root, sysname)
377 sys.dtb_filename = create_dtb_for_system(sys, '%s.dtb' % sysname)
378
379Simulation.setWorkCountOptions(test_sys, options)
380Simulation.run(options, root, test_sys, FutureClass)
|