1# Copyright (c) 2010-2013, 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42# Brad Beckmann
43
| 1# Copyright (c) 2010-2013, 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42# Brad Beckmann
43
|
| 44from __future__ import print_function
45
|
44import optparse
45import sys
46
47import m5
48from m5.defines import buildEnv
49from m5.objects import *
50from m5.util import addToPath, fatal, warn
51from m5.util.fdthelper import *
52
53addToPath('../')
54
55from ruby import Ruby
56
57from common.FSConfig import *
58from common.SysPaths import *
59from common.Benchmarks import *
60from common import Simulation
61from common import CacheConfig
62from common import MemConfig
63from common import CpuConfig
64from common.Caches import *
65from common import Options
66
67
68# Check if KVM support has been enabled, we might need to do VM
69# configuration if that's the case.
70have_kvm_support = 'BaseKvmCPU' in globals()
71def is_kvm_cpu(cpu_class):
72 return have_kvm_support and cpu_class != None and \
73 issubclass(cpu_class, BaseKvmCPU)
74
75def cmd_line_template():
76 if options.command_line and options.command_line_file:
| 46import optparse
47import sys
48
49import m5
50from m5.defines import buildEnv
51from m5.objects import *
52from m5.util import addToPath, fatal, warn
53from m5.util.fdthelper import *
54
55addToPath('../')
56
57from ruby import Ruby
58
59from common.FSConfig import *
60from common.SysPaths import *
61from common.Benchmarks import *
62from common import Simulation
63from common import CacheConfig
64from common import MemConfig
65from common import CpuConfig
66from common.Caches import *
67from common import Options
68
69
70# Check if KVM support has been enabled, we might need to do VM
71# configuration if that's the case.
72have_kvm_support = 'BaseKvmCPU' in globals()
73def is_kvm_cpu(cpu_class):
74 return have_kvm_support and cpu_class != None and \
75 issubclass(cpu_class, BaseKvmCPU)
76
77def cmd_line_template():
78 if options.command_line and options.command_line_file:
|
77 print "Error: --command-line and --command-line-file are " \
78 "mutually exclusive"
| 79 print("Error: --command-line and --command-line-file are "
80 "mutually exclusive")
|
79 sys.exit(1)
80 if options.command_line:
81 return options.command_line
82 if options.command_line_file:
83 return open(options.command_line_file).read().strip()
84 return None
85
86def build_test_system(np):
87 cmdline = cmd_line_template()
88 if buildEnv['TARGET_ISA'] == "alpha":
89 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
90 cmdline=cmdline)
91 elif buildEnv['TARGET_ISA'] == "mips":
92 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
93 elif buildEnv['TARGET_ISA'] == "sparc":
94 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
95 elif buildEnv['TARGET_ISA'] == "x86":
96 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
97 options.ruby, cmdline=cmdline)
98 elif buildEnv['TARGET_ISA'] == "arm":
99 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
100 options.num_cpus, bm[0], options.dtb_filename,
101 bare_metal=options.bare_metal,
102 cmdline=cmdline,
103 ignore_dtb=options.generate_dtb,
104 external_memory=
105 options.external_memory_system,
106 ruby=options.ruby,
107 security=options.enable_security_extensions)
108 if options.enable_context_switch_stats_dump:
109 test_sys.enable_context_switch_stats_dump = True
110 else:
111 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
112
113 # Set the cache line size for the entire system
114 test_sys.cache_line_size = options.cacheline_size
115
116 # Create a top-level voltage domain
117 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
118
119 # Create a source clock for the system and set the clock period
120 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
121 voltage_domain = test_sys.voltage_domain)
122
123 # Create a CPU voltage domain
124 test_sys.cpu_voltage_domain = VoltageDomain()
125
126 # Create a source clock for the CPUs and set the clock period
127 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
128 voltage_domain =
129 test_sys.cpu_voltage_domain)
130
131 if options.kernel is not None:
132 test_sys.kernel = binary(options.kernel)
133
134 if options.script is not None:
135 test_sys.readfile = options.script
136
137 if options.lpae:
138 test_sys.have_lpae = True
139
140 if options.virtualisation:
141 test_sys.have_virtualization = True
142
143 test_sys.init_param = options.init_param
144
145 # For now, assign all the CPUs to the same clock domain
146 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
147 for i in xrange(np)]
148
149 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
150 test_sys.kvm_vm = KvmVM()
151
152 if options.ruby:
153 Ruby.create_system(options, True, test_sys, test_sys.iobus,
154 test_sys._dma_ports)
155
156 # Create a seperate clock domain for Ruby
157 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
158 voltage_domain = test_sys.voltage_domain)
159
160 # Connect the ruby io port to the PIO bus,
161 # assuming that there is just one such port.
162 test_sys.iobus.master = test_sys.ruby._io_port.slave
163
164 for (i, cpu) in enumerate(test_sys.cpu):
165 #
166 # Tie the cpu ports to the correct ruby system ports
167 #
168 cpu.clk_domain = test_sys.cpu_clk_domain
169 cpu.createThreads()
170 cpu.createInterruptController()
171
172 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
173 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
174
175 if buildEnv['TARGET_ISA'] in ("x86", "arm"):
176 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
177 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
178
179 if buildEnv['TARGET_ISA'] in "x86":
180 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
181 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
182 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
183
184 else:
185 if options.caches or options.l2cache:
186 # By default the IOCache runs at the system clock
187 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
188 test_sys.iocache.cpu_side = test_sys.iobus.master
189 test_sys.iocache.mem_side = test_sys.membus.slave
190 elif not options.external_memory_system:
191 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
192 test_sys.iobridge.slave = test_sys.iobus.master
193 test_sys.iobridge.master = test_sys.membus.slave
194
195 # Sanity check
196 if options.fastmem:
197 if TestCPUClass != AtomicSimpleCPU:
198 fatal("Fastmem can only be used with atomic CPU!")
199 if (options.caches or options.l2cache):
200 fatal("You cannot use fastmem in combination with caches!")
201
202 if options.simpoint_profile:
203 if not options.fastmem:
204 # Atomic CPU checked with fastmem option already
205 fatal("SimPoint generation should be done with atomic cpu and fastmem")
206 if np > 1:
207 fatal("SimPoint generation not supported with more than one CPUs")
208
209 for i in xrange(np):
210 if options.fastmem:
211 test_sys.cpu[i].fastmem = True
212 if options.simpoint_profile:
213 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
214 if options.checker:
215 test_sys.cpu[i].addCheckerCpu()
216 test_sys.cpu[i].createThreads()
217
218 # If elastic tracing is enabled when not restoring from checkpoint and
219 # when not fast forwarding using the atomic cpu, then check that the
220 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
221 # passes then attach the elastic trace probe.
222 # If restoring from checkpoint or fast forwarding, the code that does this for
223 # FutureCPUClass is in the Simulation module. If the check passes then the
224 # elastic trace probe is attached to the switch CPUs.
225 if options.elastic_trace_en and options.checkpoint_restore == None and \
226 not options.fast_forward:
227 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
228
229 CacheConfig.config_cache(options, test_sys)
230
231 MemConfig.config_mem(options, test_sys)
232
233 return test_sys
234
235def build_drive_system(np):
236 # driver system CPU is always simple, so is the memory
237 # Note this is an assignment of a class, not an instance.
238 DriveCPUClass = AtomicSimpleCPU
239 drive_mem_mode = 'atomic'
240 DriveMemClass = SimpleMemory
241
242 cmdline = cmd_line_template()
243 if buildEnv['TARGET_ISA'] == 'alpha':
244 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline)
245 elif buildEnv['TARGET_ISA'] == 'mips':
246 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
247 elif buildEnv['TARGET_ISA'] == 'sparc':
248 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
249 elif buildEnv['TARGET_ISA'] == 'x86':
250 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
251 cmdline=cmdline)
252 elif buildEnv['TARGET_ISA'] == 'arm':
253 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
254 bm[1], options.dtb_filename, cmdline=cmdline,
255 ignore_dtb=options.generate_dtb)
256
257 # Create a top-level voltage domain
258 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
259
260 # Create a source clock for the system and set the clock period
261 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
262 voltage_domain = drive_sys.voltage_domain)
263
264 # Create a CPU voltage domain
265 drive_sys.cpu_voltage_domain = VoltageDomain()
266
267 # Create a source clock for the CPUs and set the clock period
268 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
269 voltage_domain =
270 drive_sys.cpu_voltage_domain)
271
272 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
273 cpu_id=0)
274 drive_sys.cpu.createThreads()
275 drive_sys.cpu.createInterruptController()
276 drive_sys.cpu.connectAllPorts(drive_sys.membus)
277 if options.fastmem:
278 drive_sys.cpu.fastmem = True
279 if options.kernel is not None:
280 drive_sys.kernel = binary(options.kernel)
281
282 if is_kvm_cpu(DriveCPUClass):
283 drive_sys.kvm_vm = KvmVM()
284
285 drive_sys.iobridge = Bridge(delay='50ns',
286 ranges = drive_sys.mem_ranges)
287 drive_sys.iobridge.slave = drive_sys.iobus.master
288 drive_sys.iobridge.master = drive_sys.membus.slave
289
290 # Create the appropriate memory controllers and connect them to the
291 # memory bus
292 drive_sys.mem_ctrls = [DriveMemClass(range = r)
293 for r in drive_sys.mem_ranges]
294 for i in xrange(len(drive_sys.mem_ctrls)):
295 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
296
297 drive_sys.init_param = options.init_param
298
299 return drive_sys
300
301# Add options
302parser = optparse.OptionParser()
303Options.addCommonOptions(parser)
304Options.addFSOptions(parser)
305
306# Add the ruby specific and protocol specific options
307if '--ruby' in sys.argv:
308 Ruby.define_options(parser)
309
310(options, args) = parser.parse_args()
311
312if args:
| 81 sys.exit(1)
82 if options.command_line:
83 return options.command_line
84 if options.command_line_file:
85 return open(options.command_line_file).read().strip()
86 return None
87
88def build_test_system(np):
89 cmdline = cmd_line_template()
90 if buildEnv['TARGET_ISA'] == "alpha":
91 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
92 cmdline=cmdline)
93 elif buildEnv['TARGET_ISA'] == "mips":
94 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
95 elif buildEnv['TARGET_ISA'] == "sparc":
96 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
97 elif buildEnv['TARGET_ISA'] == "x86":
98 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
99 options.ruby, cmdline=cmdline)
100 elif buildEnv['TARGET_ISA'] == "arm":
101 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
102 options.num_cpus, bm[0], options.dtb_filename,
103 bare_metal=options.bare_metal,
104 cmdline=cmdline,
105 ignore_dtb=options.generate_dtb,
106 external_memory=
107 options.external_memory_system,
108 ruby=options.ruby,
109 security=options.enable_security_extensions)
110 if options.enable_context_switch_stats_dump:
111 test_sys.enable_context_switch_stats_dump = True
112 else:
113 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
114
115 # Set the cache line size for the entire system
116 test_sys.cache_line_size = options.cacheline_size
117
118 # Create a top-level voltage domain
119 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
120
121 # Create a source clock for the system and set the clock period
122 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
123 voltage_domain = test_sys.voltage_domain)
124
125 # Create a CPU voltage domain
126 test_sys.cpu_voltage_domain = VoltageDomain()
127
128 # Create a source clock for the CPUs and set the clock period
129 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
130 voltage_domain =
131 test_sys.cpu_voltage_domain)
132
133 if options.kernel is not None:
134 test_sys.kernel = binary(options.kernel)
135
136 if options.script is not None:
137 test_sys.readfile = options.script
138
139 if options.lpae:
140 test_sys.have_lpae = True
141
142 if options.virtualisation:
143 test_sys.have_virtualization = True
144
145 test_sys.init_param = options.init_param
146
147 # For now, assign all the CPUs to the same clock domain
148 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
149 for i in xrange(np)]
150
151 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
152 test_sys.kvm_vm = KvmVM()
153
154 if options.ruby:
155 Ruby.create_system(options, True, test_sys, test_sys.iobus,
156 test_sys._dma_ports)
157
158 # Create a seperate clock domain for Ruby
159 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
160 voltage_domain = test_sys.voltage_domain)
161
162 # Connect the ruby io port to the PIO bus,
163 # assuming that there is just one such port.
164 test_sys.iobus.master = test_sys.ruby._io_port.slave
165
166 for (i, cpu) in enumerate(test_sys.cpu):
167 #
168 # Tie the cpu ports to the correct ruby system ports
169 #
170 cpu.clk_domain = test_sys.cpu_clk_domain
171 cpu.createThreads()
172 cpu.createInterruptController()
173
174 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
175 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
176
177 if buildEnv['TARGET_ISA'] in ("x86", "arm"):
178 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
179 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
180
181 if buildEnv['TARGET_ISA'] in "x86":
182 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
183 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
184 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
185
186 else:
187 if options.caches or options.l2cache:
188 # By default the IOCache runs at the system clock
189 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
190 test_sys.iocache.cpu_side = test_sys.iobus.master
191 test_sys.iocache.mem_side = test_sys.membus.slave
192 elif not options.external_memory_system:
193 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
194 test_sys.iobridge.slave = test_sys.iobus.master
195 test_sys.iobridge.master = test_sys.membus.slave
196
197 # Sanity check
198 if options.fastmem:
199 if TestCPUClass != AtomicSimpleCPU:
200 fatal("Fastmem can only be used with atomic CPU!")
201 if (options.caches or options.l2cache):
202 fatal("You cannot use fastmem in combination with caches!")
203
204 if options.simpoint_profile:
205 if not options.fastmem:
206 # Atomic CPU checked with fastmem option already
207 fatal("SimPoint generation should be done with atomic cpu and fastmem")
208 if np > 1:
209 fatal("SimPoint generation not supported with more than one CPUs")
210
211 for i in xrange(np):
212 if options.fastmem:
213 test_sys.cpu[i].fastmem = True
214 if options.simpoint_profile:
215 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
216 if options.checker:
217 test_sys.cpu[i].addCheckerCpu()
218 test_sys.cpu[i].createThreads()
219
220 # If elastic tracing is enabled when not restoring from checkpoint and
221 # when not fast forwarding using the atomic cpu, then check that the
222 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
223 # passes then attach the elastic trace probe.
224 # If restoring from checkpoint or fast forwarding, the code that does this for
225 # FutureCPUClass is in the Simulation module. If the check passes then the
226 # elastic trace probe is attached to the switch CPUs.
227 if options.elastic_trace_en and options.checkpoint_restore == None and \
228 not options.fast_forward:
229 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
230
231 CacheConfig.config_cache(options, test_sys)
232
233 MemConfig.config_mem(options, test_sys)
234
235 return test_sys
236
237def build_drive_system(np):
238 # driver system CPU is always simple, so is the memory
239 # Note this is an assignment of a class, not an instance.
240 DriveCPUClass = AtomicSimpleCPU
241 drive_mem_mode = 'atomic'
242 DriveMemClass = SimpleMemory
243
244 cmdline = cmd_line_template()
245 if buildEnv['TARGET_ISA'] == 'alpha':
246 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline)
247 elif buildEnv['TARGET_ISA'] == 'mips':
248 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
249 elif buildEnv['TARGET_ISA'] == 'sparc':
250 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
251 elif buildEnv['TARGET_ISA'] == 'x86':
252 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
253 cmdline=cmdline)
254 elif buildEnv['TARGET_ISA'] == 'arm':
255 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
256 bm[1], options.dtb_filename, cmdline=cmdline,
257 ignore_dtb=options.generate_dtb)
258
259 # Create a top-level voltage domain
260 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
261
262 # Create a source clock for the system and set the clock period
263 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
264 voltage_domain = drive_sys.voltage_domain)
265
266 # Create a CPU voltage domain
267 drive_sys.cpu_voltage_domain = VoltageDomain()
268
269 # Create a source clock for the CPUs and set the clock period
270 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
271 voltage_domain =
272 drive_sys.cpu_voltage_domain)
273
274 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
275 cpu_id=0)
276 drive_sys.cpu.createThreads()
277 drive_sys.cpu.createInterruptController()
278 drive_sys.cpu.connectAllPorts(drive_sys.membus)
279 if options.fastmem:
280 drive_sys.cpu.fastmem = True
281 if options.kernel is not None:
282 drive_sys.kernel = binary(options.kernel)
283
284 if is_kvm_cpu(DriveCPUClass):
285 drive_sys.kvm_vm = KvmVM()
286
287 drive_sys.iobridge = Bridge(delay='50ns',
288 ranges = drive_sys.mem_ranges)
289 drive_sys.iobridge.slave = drive_sys.iobus.master
290 drive_sys.iobridge.master = drive_sys.membus.slave
291
292 # Create the appropriate memory controllers and connect them to the
293 # memory bus
294 drive_sys.mem_ctrls = [DriveMemClass(range = r)
295 for r in drive_sys.mem_ranges]
296 for i in xrange(len(drive_sys.mem_ctrls)):
297 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
298
299 drive_sys.init_param = options.init_param
300
301 return drive_sys
302
303# Add options
304parser = optparse.OptionParser()
305Options.addCommonOptions(parser)
306Options.addFSOptions(parser)
307
308# Add the ruby specific and protocol specific options
309if '--ruby' in sys.argv:
310 Ruby.define_options(parser)
311
312(options, args) = parser.parse_args()
313
314if args:
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313 print "Error: script doesn't take any positional arguments"
| 315 print("Error: script doesn't take any positional arguments")
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314 sys.exit(1)
315
316# system under test can be any CPU
317(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
318
319# Match the memories with the CPUs, based on the options for the test system
320TestMemClass = Simulation.setMemClass(options)
321
322if options.benchmark:
323 try:
324 bm = Benchmarks[options.benchmark]
325 except KeyError:
| 316 sys.exit(1)
317
318# system under test can be any CPU
319(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
320
321# Match the memories with the CPUs, based on the options for the test system
322TestMemClass = Simulation.setMemClass(options)
323
324if options.benchmark:
325 try:
326 bm = Benchmarks[options.benchmark]
327 except KeyError:
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326 print "Error benchmark %s has not been defined." % options.benchmark
327 print "Valid benchmarks are: %s" % DefinedBenchmarks
| 328 print("Error benchmark %s has not been defined." % options.benchmark)
329 print("Valid benchmarks are: %s" % DefinedBenchmarks)
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328 sys.exit(1)
329else:
330 if options.dual:
331 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
332 mem=options.mem_size, os_type=options.os_type),
333 SysConfig(disk=options.disk_image, rootdev=options.root_device,
334 mem=options.mem_size, os_type=options.os_type)]
335 else:
336 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
337 mem=options.mem_size, os_type=options.os_type)]
338
339np = options.num_cpus
340
341test_sys = build_test_system(np)
342if len(bm) == 2:
343 drive_sys = build_drive_system(np)
344 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
345elif len(bm) == 1 and options.dist:
346 # This system is part of a dist-gem5 simulation
347 root = makeDistRoot(test_sys,
348 options.dist_rank,
349 options.dist_size,
350 options.dist_server_name,
351 options.dist_server_port,
352 options.dist_sync_repeat,
353 options.dist_sync_start,
354 options.ethernet_linkspeed,
355 options.ethernet_linkdelay,
356 options.etherdump);
357elif len(bm) == 1:
358 root = Root(full_system=True, system=test_sys)
359else:
| 330 sys.exit(1)
331else:
332 if options.dual:
333 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
334 mem=options.mem_size, os_type=options.os_type),
335 SysConfig(disk=options.disk_image, rootdev=options.root_device,
336 mem=options.mem_size, os_type=options.os_type)]
337 else:
338 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
339 mem=options.mem_size, os_type=options.os_type)]
340
341np = options.num_cpus
342
343test_sys = build_test_system(np)
344if len(bm) == 2:
345 drive_sys = build_drive_system(np)
346 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
347elif len(bm) == 1 and options.dist:
348 # This system is part of a dist-gem5 simulation
349 root = makeDistRoot(test_sys,
350 options.dist_rank,
351 options.dist_size,
352 options.dist_server_name,
353 options.dist_server_port,
354 options.dist_sync_repeat,
355 options.dist_sync_start,
356 options.ethernet_linkspeed,
357 options.ethernet_linkdelay,
358 options.etherdump);
359elif len(bm) == 1:
360 root = Root(full_system=True, system=test_sys)
361else:
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360 print "Error I don't know how to create more than 2 systems."
| 362 print("Error I don't know how to create more than 2 systems.")
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361 sys.exit(1)
362
363if options.timesync:
364 root.time_sync_enable = True
365
366if options.frame_capture:
367 VncServer.frame_capture = True
368
369if buildEnv['TARGET_ISA'] == "arm" and options.generate_dtb:
370 # Sanity checks
371 if options.dtb_filename:
372 fatal("--generate-dtb and --dtb-filename cannot be specified at the"\
373 "same time.")
374
375 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
376 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
377 "platforms, unless custom hardware models have been equipped "\
378 "with generation functionality.")
379
380 # Generate a Device Tree
381 def create_dtb_for_system(system, filename):
382 state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
383 rootNode = system.generateDeviceTree(state)
384
385 fdt = Fdt()
386 fdt.add_rootnode(rootNode)
387 dtb_filename = os.path.join(m5.options.outdir, filename)
388 return fdt.writeDtbFile(dtb_filename)
389
390 for sysname in ('system', 'testsys', 'drivesys'):
391 if hasattr(root, sysname):
392 sys = getattr(root, sysname)
393 sys.dtb_filename = create_dtb_for_system(sys, '%s.dtb' % sysname)
394
395Simulation.setWorkCountOptions(test_sys, options)
396Simulation.run(options, root, test_sys, FutureClass)
| 363 sys.exit(1)
364
365if options.timesync:
366 root.time_sync_enable = True
367
368if options.frame_capture:
369 VncServer.frame_capture = True
370
371if buildEnv['TARGET_ISA'] == "arm" and options.generate_dtb:
372 # Sanity checks
373 if options.dtb_filename:
374 fatal("--generate-dtb and --dtb-filename cannot be specified at the"\
375 "same time.")
376
377 if options.machine_type not in ["VExpress_GEM5", "VExpress_GEM5_V1"]:
378 warn("Can only correctly generate a dtb for VExpress_GEM5_V1 " \
379 "platforms, unless custom hardware models have been equipped "\
380 "with generation functionality.")
381
382 # Generate a Device Tree
383 def create_dtb_for_system(system, filename):
384 state = FdtState(addr_cells=2, size_cells=2, cpu_cells=1)
385 rootNode = system.generateDeviceTree(state)
386
387 fdt = Fdt()
388 fdt.add_rootnode(rootNode)
389 dtb_filename = os.path.join(m5.options.outdir, filename)
390 return fdt.writeDtbFile(dtb_filename)
391
392 for sysname in ('system', 'testsys', 'drivesys'):
393 if hasattr(root, sysname):
394 sys = getattr(root, sysname)
395 sys.dtb_filename = create_dtb_for_system(sys, '%s.dtb' % sysname)
396
397Simulation.setWorkCountOptions(test_sys, options)
398Simulation.run(options, root, test_sys, FutureClass)
|