1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42# Brad Beckmann
43
44import optparse
45import sys
46
47import m5
48from m5.defines import buildEnv
49from m5.objects import *
50from m5.util import addToPath, fatal
51
52addToPath('../common')
53addToPath('../ruby')
54
55import Ruby
56
57from FSConfig import *
58from SysPaths import *
59from Benchmarks import *
60import Simulation
61import CacheConfig
62import MemConfig
63from Caches import *
64import Options
65
66
67# Check if KVM support has been enabled, we might need to do VM
68# configuration if that's the case.
69have_kvm_support = 'BaseKvmCPU' in globals()
70def is_kvm_cpu(cpu_class):
71 return have_kvm_support and cpu_class != None and \
72 issubclass(cpu_class, BaseKvmCPU)
73
74def build_test_system(np):
75 if buildEnv['TARGET_ISA'] == "alpha":
76 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
77 elif buildEnv['TARGET_ISA'] == "mips":
78 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
79 elif buildEnv['TARGET_ISA'] == "sparc":
80 test_sys = makeSparcSystem(test_mem_mode, bm[0])
81 elif buildEnv['TARGET_ISA'] == "x86":
82 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
83 options.ruby)
84 elif buildEnv['TARGET_ISA'] == "arm":
85 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
86 options.num_cpus, bm[0], options.dtb_filename,
87 bare_metal=options.bare_metal)
88 if options.enable_context_switch_stats_dump:
89 test_sys.enable_context_switch_stats_dump = True
90 else:
91 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
92
93 # Set the cache line size for the entire system
94 test_sys.cache_line_size = options.cacheline_size
95
96 # Create a top-level voltage domain
97 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
98
99 # Create a source clock for the system and set the clock period
100 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
101 voltage_domain = test_sys.voltage_domain)
102
103 # Create a CPU voltage domain
104 test_sys.cpu_voltage_domain = VoltageDomain()
105
106 # Create a source clock for the CPUs and set the clock period
107 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
108 voltage_domain =
109 test_sys.cpu_voltage_domain)
110
111 if options.kernel is not None:
112 test_sys.kernel = binary(options.kernel)
113
114 if options.script is not None:
115 test_sys.readfile = options.script
116
117 if options.lpae:
118 test_sys.have_lpae = True
119
120 if options.virtualisation:
121 test_sys.have_virtualization = True
122
123 test_sys.init_param = options.init_param
124
125 # For now, assign all the CPUs to the same clock domain
126 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
127 for i in xrange(np)]
128
129 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
130 test_sys.vm = KvmVM()
131
132 if options.ruby:
133 # Check for timing mode because ruby does not support atomic accesses
134 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
135 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
136 sys.exit(1)
137
| 1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42# Brad Beckmann
43
44import optparse
45import sys
46
47import m5
48from m5.defines import buildEnv
49from m5.objects import *
50from m5.util import addToPath, fatal
51
52addToPath('../common')
53addToPath('../ruby')
54
55import Ruby
56
57from FSConfig import *
58from SysPaths import *
59from Benchmarks import *
60import Simulation
61import CacheConfig
62import MemConfig
63from Caches import *
64import Options
65
66
67# Check if KVM support has been enabled, we might need to do VM
68# configuration if that's the case.
69have_kvm_support = 'BaseKvmCPU' in globals()
70def is_kvm_cpu(cpu_class):
71 return have_kvm_support and cpu_class != None and \
72 issubclass(cpu_class, BaseKvmCPU)
73
74def build_test_system(np):
75 if buildEnv['TARGET_ISA'] == "alpha":
76 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
77 elif buildEnv['TARGET_ISA'] == "mips":
78 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
79 elif buildEnv['TARGET_ISA'] == "sparc":
80 test_sys = makeSparcSystem(test_mem_mode, bm[0])
81 elif buildEnv['TARGET_ISA'] == "x86":
82 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
83 options.ruby)
84 elif buildEnv['TARGET_ISA'] == "arm":
85 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
86 options.num_cpus, bm[0], options.dtb_filename,
87 bare_metal=options.bare_metal)
88 if options.enable_context_switch_stats_dump:
89 test_sys.enable_context_switch_stats_dump = True
90 else:
91 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
92
93 # Set the cache line size for the entire system
94 test_sys.cache_line_size = options.cacheline_size
95
96 # Create a top-level voltage domain
97 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
98
99 # Create a source clock for the system and set the clock period
100 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
101 voltage_domain = test_sys.voltage_domain)
102
103 # Create a CPU voltage domain
104 test_sys.cpu_voltage_domain = VoltageDomain()
105
106 # Create a source clock for the CPUs and set the clock period
107 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
108 voltage_domain =
109 test_sys.cpu_voltage_domain)
110
111 if options.kernel is not None:
112 test_sys.kernel = binary(options.kernel)
113
114 if options.script is not None:
115 test_sys.readfile = options.script
116
117 if options.lpae:
118 test_sys.have_lpae = True
119
120 if options.virtualisation:
121 test_sys.have_virtualization = True
122
123 test_sys.init_param = options.init_param
124
125 # For now, assign all the CPUs to the same clock domain
126 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
127 for i in xrange(np)]
128
129 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
130 test_sys.vm = KvmVM()
131
132 if options.ruby:
133 # Check for timing mode because ruby does not support atomic accesses
134 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
135 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
136 sys.exit(1)
137
|
138 Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
| 138 Ruby.create_system(options, True, test_sys, test_sys.iobus,
139 test_sys._dma_ports)
140 test_sys.physmem = [SimpleMemory(range = r, null = True)
141 for r in test_sys.mem_ranges]
|
139
140 # Create a seperate clock domain for Ruby
141 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
142 voltage_domain = test_sys.voltage_domain)
143
144 for (i, cpu) in enumerate(test_sys.cpu):
145 #
146 # Tie the cpu ports to the correct ruby system ports
147 #
148 cpu.clk_domain = test_sys.cpu_clk_domain
149 cpu.createThreads()
150 cpu.createInterruptController()
151
152 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
153 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
154
155 if buildEnv['TARGET_ISA'] == "x86":
156 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
157 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
158
159 cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
160 cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
161 cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
162
| 142
143 # Create a seperate clock domain for Ruby
144 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
145 voltage_domain = test_sys.voltage_domain)
146
147 for (i, cpu) in enumerate(test_sys.cpu):
148 #
149 # Tie the cpu ports to the correct ruby system ports
150 #
151 cpu.clk_domain = test_sys.cpu_clk_domain
152 cpu.createThreads()
153 cpu.createInterruptController()
154
155 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
156 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
157
158 if buildEnv['TARGET_ISA'] == "x86":
159 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
160 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
161
162 cpu.interrupts.pio = test_sys.ruby._cpu_ports[i].master
163 cpu.interrupts.int_master = test_sys.ruby._cpu_ports[i].slave
164 cpu.interrupts.int_slave = test_sys.ruby._cpu_ports[i].master
165
|
163 test_sys.ruby._cpu_ports[i].access_phys_mem = True
| 166 # Connect the ruby io port to the PIO bus,
167 # assuming that there is just one such port.
168 test_sys.iobus.master = test_sys.ruby._io_port.slave
|
164
| 169
|
165 # Create the appropriate memory controllers
166 # and connect them to the IO bus
167 test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
168 for i in xrange(len(test_sys.mem_ctrls)):
169 test_sys.mem_ctrls[i].port = test_sys.iobus.master
170
| |
171 else:
172 if options.caches or options.l2cache:
173 # By default the IOCache runs at the system clock
174 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
175 test_sys.iocache.cpu_side = test_sys.iobus.master
176 test_sys.iocache.mem_side = test_sys.membus.slave
177 else:
178 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
179 test_sys.iobridge.slave = test_sys.iobus.master
180 test_sys.iobridge.master = test_sys.membus.slave
181
182 # Sanity check
183 if options.fastmem:
184 if TestCPUClass != AtomicSimpleCPU:
185 fatal("Fastmem can only be used with atomic CPU!")
186 if (options.caches or options.l2cache):
187 fatal("You cannot use fastmem in combination with caches!")
188
189 for i in xrange(np):
190 if options.fastmem:
191 test_sys.cpu[i].fastmem = True
192 if options.checker:
193 test_sys.cpu[i].addCheckerCpu()
194 test_sys.cpu[i].createThreads()
195
196 CacheConfig.config_cache(options, test_sys)
197 MemConfig.config_mem(options, test_sys)
198
199 return test_sys
200
201def build_drive_system(np):
202 # driver system CPU is always simple, so is the memory
203 # Note this is an assignment of a class, not an instance.
204 DriveCPUClass = AtomicSimpleCPU
205 drive_mem_mode = 'atomic'
206 DriveMemClass = SimpleMemory
207
208 if buildEnv['TARGET_ISA'] == 'alpha':
209 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
210 elif buildEnv['TARGET_ISA'] == 'mips':
211 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
212 elif buildEnv['TARGET_ISA'] == 'sparc':
213 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
214 elif buildEnv['TARGET_ISA'] == 'x86':
215 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1])
216 elif buildEnv['TARGET_ISA'] == 'arm':
217 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
218
219 # Create a top-level voltage domain
220 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
221
222 # Create a source clock for the system and set the clock period
223 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
224 voltage_domain = drive_sys.voltage_domain)
225
226 # Create a CPU voltage domain
227 drive_sys.cpu_voltage_domain = VoltageDomain()
228
229 # Create a source clock for the CPUs and set the clock period
230 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
231 voltage_domain =
232 drive_sys.cpu_voltage_domain)
233
234 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
235 cpu_id=0)
236 drive_sys.cpu.createThreads()
237 drive_sys.cpu.createInterruptController()
238 drive_sys.cpu.connectAllPorts(drive_sys.membus)
239 if options.fastmem:
240 drive_sys.cpu.fastmem = True
241 if options.kernel is not None:
242 drive_sys.kernel = binary(options.kernel)
243
244 if is_kvm_cpu(DriveCPUClass):
245 drive_sys.vm = KvmVM()
246
247 drive_sys.iobridge = Bridge(delay='50ns',
248 ranges = drive_sys.mem_ranges)
249 drive_sys.iobridge.slave = drive_sys.iobus.master
250 drive_sys.iobridge.master = drive_sys.membus.slave
251
252 # Create the appropriate memory controllers and connect them to the
253 # memory bus
254 drive_sys.mem_ctrls = [DriveMemClass(range = r)
255 for r in drive_sys.mem_ranges]
256 for i in xrange(len(drive_sys.mem_ctrls)):
257 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
258
259 drive_sys.init_param = options.init_param
260
261 return drive_sys
262
263# Add options
264parser = optparse.OptionParser()
265Options.addCommonOptions(parser)
266Options.addFSOptions(parser)
267
268# Add the ruby specific and protocol specific options
269if '--ruby' in sys.argv:
270 Ruby.define_options(parser)
271
272(options, args) = parser.parse_args()
273
274if args:
275 print "Error: script doesn't take any positional arguments"
276 sys.exit(1)
277
278# system under test can be any CPU
279(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
280
281# Match the memories with the CPUs, based on the options for the test system
282TestMemClass = Simulation.setMemClass(options)
283
284if options.benchmark:
285 try:
286 bm = Benchmarks[options.benchmark]
287 except KeyError:
288 print "Error benchmark %s has not been defined." % options.benchmark
289 print "Valid benchmarks are: %s" % DefinedBenchmarks
290 sys.exit(1)
291else:
292 if options.dual:
293 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
294 SysConfig(disk=options.disk_image, mem=options.mem_size)]
295 else:
296 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
297
298np = options.num_cpus
299
300test_sys = build_test_system(np)
301if len(bm) == 2:
302 drive_sys = build_drive_system(np)
303 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
304elif len(bm) == 1:
305 root = Root(full_system=True, system=test_sys)
306else:
307 print "Error I don't know how to create more than 2 systems."
308 sys.exit(1)
309
310if options.timesync:
311 root.time_sync_enable = True
312
313if options.frame_capture:
314 VncServer.frame_capture = True
315
316Simulation.setWorkCountOptions(test_sys, options)
317Simulation.run(options, root, test_sys, FutureClass)
| 170 else:
171 if options.caches or options.l2cache:
172 # By default the IOCache runs at the system clock
173 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
174 test_sys.iocache.cpu_side = test_sys.iobus.master
175 test_sys.iocache.mem_side = test_sys.membus.slave
176 else:
177 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
178 test_sys.iobridge.slave = test_sys.iobus.master
179 test_sys.iobridge.master = test_sys.membus.slave
180
181 # Sanity check
182 if options.fastmem:
183 if TestCPUClass != AtomicSimpleCPU:
184 fatal("Fastmem can only be used with atomic CPU!")
185 if (options.caches or options.l2cache):
186 fatal("You cannot use fastmem in combination with caches!")
187
188 for i in xrange(np):
189 if options.fastmem:
190 test_sys.cpu[i].fastmem = True
191 if options.checker:
192 test_sys.cpu[i].addCheckerCpu()
193 test_sys.cpu[i].createThreads()
194
195 CacheConfig.config_cache(options, test_sys)
196 MemConfig.config_mem(options, test_sys)
197
198 return test_sys
199
200def build_drive_system(np):
201 # driver system CPU is always simple, so is the memory
202 # Note this is an assignment of a class, not an instance.
203 DriveCPUClass = AtomicSimpleCPU
204 drive_mem_mode = 'atomic'
205 DriveMemClass = SimpleMemory
206
207 if buildEnv['TARGET_ISA'] == 'alpha':
208 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
209 elif buildEnv['TARGET_ISA'] == 'mips':
210 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
211 elif buildEnv['TARGET_ISA'] == 'sparc':
212 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
213 elif buildEnv['TARGET_ISA'] == 'x86':
214 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1])
215 elif buildEnv['TARGET_ISA'] == 'arm':
216 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
217
218 # Create a top-level voltage domain
219 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
220
221 # Create a source clock for the system and set the clock period
222 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
223 voltage_domain = drive_sys.voltage_domain)
224
225 # Create a CPU voltage domain
226 drive_sys.cpu_voltage_domain = VoltageDomain()
227
228 # Create a source clock for the CPUs and set the clock period
229 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
230 voltage_domain =
231 drive_sys.cpu_voltage_domain)
232
233 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
234 cpu_id=0)
235 drive_sys.cpu.createThreads()
236 drive_sys.cpu.createInterruptController()
237 drive_sys.cpu.connectAllPorts(drive_sys.membus)
238 if options.fastmem:
239 drive_sys.cpu.fastmem = True
240 if options.kernel is not None:
241 drive_sys.kernel = binary(options.kernel)
242
243 if is_kvm_cpu(DriveCPUClass):
244 drive_sys.vm = KvmVM()
245
246 drive_sys.iobridge = Bridge(delay='50ns',
247 ranges = drive_sys.mem_ranges)
248 drive_sys.iobridge.slave = drive_sys.iobus.master
249 drive_sys.iobridge.master = drive_sys.membus.slave
250
251 # Create the appropriate memory controllers and connect them to the
252 # memory bus
253 drive_sys.mem_ctrls = [DriveMemClass(range = r)
254 for r in drive_sys.mem_ranges]
255 for i in xrange(len(drive_sys.mem_ctrls)):
256 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
257
258 drive_sys.init_param = options.init_param
259
260 return drive_sys
261
262# Add options
263parser = optparse.OptionParser()
264Options.addCommonOptions(parser)
265Options.addFSOptions(parser)
266
267# Add the ruby specific and protocol specific options
268if '--ruby' in sys.argv:
269 Ruby.define_options(parser)
270
271(options, args) = parser.parse_args()
272
273if args:
274 print "Error: script doesn't take any positional arguments"
275 sys.exit(1)
276
277# system under test can be any CPU
278(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
279
280# Match the memories with the CPUs, based on the options for the test system
281TestMemClass = Simulation.setMemClass(options)
282
283if options.benchmark:
284 try:
285 bm = Benchmarks[options.benchmark]
286 except KeyError:
287 print "Error benchmark %s has not been defined." % options.benchmark
288 print "Valid benchmarks are: %s" % DefinedBenchmarks
289 sys.exit(1)
290else:
291 if options.dual:
292 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
293 SysConfig(disk=options.disk_image, mem=options.mem_size)]
294 else:
295 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
296
297np = options.num_cpus
298
299test_sys = build_test_system(np)
300if len(bm) == 2:
301 drive_sys = build_drive_system(np)
302 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
303elif len(bm) == 1:
304 root = Root(full_system=True, system=test_sys)
305else:
306 print "Error I don't know how to create more than 2 systems."
307 sys.exit(1)
308
309if options.timesync:
310 root.time_sync_enable = True
311
312if options.frame_capture:
313 VncServer.frame_capture = True
314
315Simulation.setWorkCountOptions(test_sys, options)
316Simulation.run(options, root, test_sys, FutureClass)
|