1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
| 1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
|
| 13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
|
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright
21# notice, this list of conditions and the following disclaimer in the
22# documentation and/or other materials provided with the distribution;
23# neither the name of the copyright holders nor the names of its
24# contributors may be used to endorse or promote products derived from
25# this software without specific prior written permission.
26#
27# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
28# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
29# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
30# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
31# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
| 15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
|
| 42# Brad Beckmann
|
40
41import optparse
42import sys
43
44import m5
45from m5.defines import buildEnv
46from m5.objects import *
47from m5.util import addToPath, fatal
48
49addToPath('../common')
| 43
44import optparse
45import sys
46
47import m5
48from m5.defines import buildEnv
49from m5.objects import *
50from m5.util import addToPath, fatal
51
52addToPath('../common')
|
| 53addToPath('../ruby')
|
50
| 54
|
| 55import Ruby
56
|
51from FSConfig import *
52from SysPaths import *
53from Benchmarks import *
54import Simulation
55import CacheConfig
56import MemConfig
57from Caches import *
58import Options
59
60parser = optparse.OptionParser()
61Options.addCommonOptions(parser)
62Options.addFSOptions(parser)
63
| 57from FSConfig import *
58from SysPaths import *
59from Benchmarks import *
60import Simulation
61import CacheConfig
62import MemConfig
63from Caches import *
64import Options
65
66parser = optparse.OptionParser()
67Options.addCommonOptions(parser)
68Options.addFSOptions(parser)
69
|
| 70# Add the ruby specific and protocol specific options
71if '--ruby' in sys.argv:
72 Ruby.define_options(parser)
73
|
64(options, args) = parser.parse_args()
65
66if args:
67 print "Error: script doesn't take any positional arguments"
68 sys.exit(1)
69
70# driver system CPU is always simple... note this is an assignment of
71# a class, not an instance.
72DriveCPUClass = AtomicSimpleCPU
73drive_mem_mode = 'atomic'
74
75# Check if KVM support has been enabled, we might need to do VM
76# configuration if that's the case.
77have_kvm_support = 'BaseKvmCPU' in globals()
78def is_kvm_cpu(cpu_class):
79 return have_kvm_support and cpu_class != None and \
80 issubclass(cpu_class, BaseKvmCPU)
81
82# system under test can be any CPU
83(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
84
85# Match the memories with the CPUs, the driver system always simple,
86# and based on the options for the test system
87DriveMemClass = SimpleMemory
88TestMemClass = Simulation.setMemClass(options)
89
90if options.benchmark:
91 try:
92 bm = Benchmarks[options.benchmark]
93 except KeyError:
94 print "Error benchmark %s has not been defined." % options.benchmark
95 print "Valid benchmarks are: %s" % DefinedBenchmarks
96 sys.exit(1)
97else:
98 if options.dual:
99 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
100 SysConfig(disk=options.disk_image, mem=options.mem_size)]
101 else:
102 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
103
104np = options.num_cpus
105
106if buildEnv['TARGET_ISA'] == "alpha":
| 74(options, args) = parser.parse_args()
75
76if args:
77 print "Error: script doesn't take any positional arguments"
78 sys.exit(1)
79
80# driver system CPU is always simple... note this is an assignment of
81# a class, not an instance.
82DriveCPUClass = AtomicSimpleCPU
83drive_mem_mode = 'atomic'
84
85# Check if KVM support has been enabled, we might need to do VM
86# configuration if that's the case.
87have_kvm_support = 'BaseKvmCPU' in globals()
88def is_kvm_cpu(cpu_class):
89 return have_kvm_support and cpu_class != None and \
90 issubclass(cpu_class, BaseKvmCPU)
91
92# system under test can be any CPU
93(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
94
95# Match the memories with the CPUs, the driver system always simple,
96# and based on the options for the test system
97DriveMemClass = SimpleMemory
98TestMemClass = Simulation.setMemClass(options)
99
100if options.benchmark:
101 try:
102 bm = Benchmarks[options.benchmark]
103 except KeyError:
104 print "Error benchmark %s has not been defined." % options.benchmark
105 print "Valid benchmarks are: %s" % DefinedBenchmarks
106 sys.exit(1)
107else:
108 if options.dual:
109 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
110 SysConfig(disk=options.disk_image, mem=options.mem_size)]
111 else:
112 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
113
114np = options.num_cpus
115
116if buildEnv['TARGET_ISA'] == "alpha":
|
107 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
| 117 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby)
|
108elif buildEnv['TARGET_ISA'] == "mips":
109 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
110elif buildEnv['TARGET_ISA'] == "sparc":
111 test_sys = makeSparcSystem(test_mem_mode, bm[0])
112elif buildEnv['TARGET_ISA'] == "x86":
| 118elif buildEnv['TARGET_ISA'] == "mips":
119 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
120elif buildEnv['TARGET_ISA'] == "sparc":
121 test_sys = makeSparcSystem(test_mem_mode, bm[0])
122elif buildEnv['TARGET_ISA'] == "x86":
|
113 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
| 123 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
124 options.ruby)
|
114elif buildEnv['TARGET_ISA'] == "arm":
115 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
116 options.dtb_filename,
117 bare_metal=options.bare_metal)
118 if options.enable_context_switch_stats_dump:
119 test_sys.enable_context_switch_stats_dump = True
120else:
121 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
122
| 125elif buildEnv['TARGET_ISA'] == "arm":
126 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
127 options.dtb_filename,
128 bare_metal=options.bare_metal)
129 if options.enable_context_switch_stats_dump:
130 test_sys.enable_context_switch_stats_dump = True
131else:
132 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
133
|
| 134# Set the cache line size for the entire system
135test_sys.cache_line_size = options.cacheline_size
136
|
123# Create a top-level voltage domain
124test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
125
126# Create a source clock for the system and set the clock period
127test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
128 voltage_domain = test_sys.voltage_domain)
129
130# Create a CPU voltage domain
131test_sys.cpu_voltage_domain = VoltageDomain()
132
133# Create a source clock for the CPUs and set the clock period
134test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
135 voltage_domain =
136 test_sys.cpu_voltage_domain)
137
138if options.kernel is not None:
139 test_sys.kernel = binary(options.kernel)
140
141if options.script is not None:
142 test_sys.readfile = options.script
143
144if options.lpae:
145 test_sys.have_lpae = True
146
147if options.virtualisation:
148 test_sys.have_virtualization = True
149
150test_sys.init_param = options.init_param
151
152# For now, assign all the CPUs to the same clock domain
153test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
154 for i in xrange(np)]
155
156if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
157 test_sys.vm = KvmVM()
158
| 137# Create a top-level voltage domain
138test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
139
140# Create a source clock for the system and set the clock period
141test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
142 voltage_domain = test_sys.voltage_domain)
143
144# Create a CPU voltage domain
145test_sys.cpu_voltage_domain = VoltageDomain()
146
147# Create a source clock for the CPUs and set the clock period
148test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
149 voltage_domain =
150 test_sys.cpu_voltage_domain)
151
152if options.kernel is not None:
153 test_sys.kernel = binary(options.kernel)
154
155if options.script is not None:
156 test_sys.readfile = options.script
157
158if options.lpae:
159 test_sys.have_lpae = True
160
161if options.virtualisation:
162 test_sys.have_virtualization = True
163
164test_sys.init_param = options.init_param
165
166# For now, assign all the CPUs to the same clock domain
167test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
168 for i in xrange(np)]
169
170if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
171 test_sys.vm = KvmVM()
172
|
159if options.caches or options.l2cache:
160 # By default the IOCache runs at the system clock
161 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
162 test_sys.iocache.cpu_side = test_sys.iobus.master
163 test_sys.iocache.mem_side = test_sys.membus.slave
164else:
165 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
166 test_sys.iobridge.slave = test_sys.iobus.master
167 test_sys.iobridge.master = test_sys.membus.slave
| 173if options.ruby:
174 # Check for timing mode because ruby does not support atomic accesses
175 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"):
176 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
177 sys.exit(1)
|
168
| 178
|
169# Sanity check
170if options.fastmem:
171 if TestCPUClass != AtomicSimpleCPU:
172 fatal("Fastmem can only be used with atomic CPU!")
173 if (options.caches or options.l2cache):
174 fatal("You cannot use fastmem in combination with caches!")
| 179 Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports)
|
175
| 180
|
176for i in xrange(np):
| 181 # Create a seperate clock domain for Ruby
182 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
183 voltage_domain = test_sys.voltage_domain)
184
185 for (i, cpu) in enumerate(test_sys.cpu):
186 #
187 # Tie the cpu ports to the correct ruby system ports
188 #
189 cpu.clk_domain = test_sys.cpu_clk_domain
190 cpu.createThreads()
191 cpu.createInterruptController()
192
193 cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave
194 cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave
195
196 if buildEnv['TARGET_ISA'] == "x86":
197 cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
198 cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave
199
200 cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master
201 cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave
202 cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master
203
204 test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True
205
206 # Create the appropriate memory controllers and connect them to the
207 # PIO bus
208 test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges]
209 for i in xrange(len(test_sys.mem_ctrls)):
210 test_sys.mem_ctrls[i].port = test_sys.iobus.master
211
212else:
213 if options.caches or options.l2cache:
214 # By default the IOCache runs at the system clock
215 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
216 test_sys.iocache.cpu_side = test_sys.iobus.master
217 test_sys.iocache.mem_side = test_sys.membus.slave
218 else:
219 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
220 test_sys.iobridge.slave = test_sys.iobus.master
221 test_sys.iobridge.master = test_sys.membus.slave
222
223 # Sanity check
|
177 if options.fastmem:
| 224 if options.fastmem:
|
178 test_sys.cpu[i].fastmem = True
179 if options.checker:
180 test_sys.cpu[i].addCheckerCpu()
181 test_sys.cpu[i].createThreads()
| 225 if TestCPUClass != AtomicSimpleCPU:
226 fatal("Fastmem can only be used with atomic CPU!")
227 if (options.caches or options.l2cache):
228 fatal("You cannot use fastmem in combination with caches!")
|
182
| 229
|
183CacheConfig.config_cache(options, test_sys)
184MemConfig.config_mem(options, test_sys)
| 230 for i in xrange(np):
231 if options.fastmem:
232 test_sys.cpu[i].fastmem = True
233 if options.checker:
234 test_sys.cpu[i].addCheckerCpu()
235 test_sys.cpu[i].createThreads()
|
185
| 236
|
| 237 CacheConfig.config_cache(options, test_sys)
238 MemConfig.config_mem(options, test_sys)
239
|
186if len(bm) == 2:
187 if buildEnv['TARGET_ISA'] == 'alpha':
188 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
189 elif buildEnv['TARGET_ISA'] == 'mips':
190 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
191 elif buildEnv['TARGET_ISA'] == 'sparc':
192 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
193 elif buildEnv['TARGET_ISA'] == 'x86':
194 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1])
195 elif buildEnv['TARGET_ISA'] == 'arm':
196 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
197
198 # Create a top-level voltage domain
199 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
200
201 # Create a source clock for the system and set the clock period
202 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
203
204 # Create a CPU voltage domain
205 drive_sys.cpu_voltage_domain = VoltageDomain()
206
207 # Create a source clock for the CPUs and set the clock period
208 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
209 voltage_domain =
210 drive_sys.cpu_voltage_domain)
211
212 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
213 cpu_id=0)
214 drive_sys.cpu.createThreads()
215 drive_sys.cpu.createInterruptController()
216 drive_sys.cpu.connectAllPorts(drive_sys.membus)
217 if options.fastmem:
218 drive_sys.cpu.fastmem = True
219 if options.kernel is not None:
220 drive_sys.kernel = binary(options.kernel)
221
222 if is_kvm_cpu(DriveCPUClass):
223 drive_sys.vm = KvmVM()
224
225 drive_sys.iobridge = Bridge(delay='50ns',
226 ranges = drive_sys.mem_ranges)
227 drive_sys.iobridge.slave = drive_sys.iobus.master
228 drive_sys.iobridge.master = drive_sys.membus.slave
229
230 # Create the appropriate memory controllers and connect them to the
231 # memory bus
232 drive_sys.mem_ctrls = [DriveMemClass(range = r)
233 for r in drive_sys.mem_ranges]
234 for i in xrange(len(drive_sys.mem_ctrls)):
235 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
236
237 drive_sys.init_param = options.init_param
238 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
239elif len(bm) == 1:
240 root = Root(full_system=True, system=test_sys)
241else:
242 print "Error I don't know how to create more than 2 systems."
243 sys.exit(1)
244
245if options.timesync:
246 root.time_sync_enable = True
247
248if options.frame_capture:
249 VncServer.frame_capture = True
250
251Simulation.setWorkCountOptions(test_sys, options)
252Simulation.run(options, root, test_sys, FutureClass)
| 240if len(bm) == 2:
241 if buildEnv['TARGET_ISA'] == 'alpha':
242 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
243 elif buildEnv['TARGET_ISA'] == 'mips':
244 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
245 elif buildEnv['TARGET_ISA'] == 'sparc':
246 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
247 elif buildEnv['TARGET_ISA'] == 'x86':
248 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1])
249 elif buildEnv['TARGET_ISA'] == 'arm':
250 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1])
251
252 # Create a top-level voltage domain
253 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
254
255 # Create a source clock for the system and set the clock period
256 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
257
258 # Create a CPU voltage domain
259 drive_sys.cpu_voltage_domain = VoltageDomain()
260
261 # Create a source clock for the CPUs and set the clock period
262 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
263 voltage_domain =
264 drive_sys.cpu_voltage_domain)
265
266 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
267 cpu_id=0)
268 drive_sys.cpu.createThreads()
269 drive_sys.cpu.createInterruptController()
270 drive_sys.cpu.connectAllPorts(drive_sys.membus)
271 if options.fastmem:
272 drive_sys.cpu.fastmem = True
273 if options.kernel is not None:
274 drive_sys.kernel = binary(options.kernel)
275
276 if is_kvm_cpu(DriveCPUClass):
277 drive_sys.vm = KvmVM()
278
279 drive_sys.iobridge = Bridge(delay='50ns',
280 ranges = drive_sys.mem_ranges)
281 drive_sys.iobridge.slave = drive_sys.iobus.master
282 drive_sys.iobridge.master = drive_sys.membus.slave
283
284 # Create the appropriate memory controllers and connect them to the
285 # memory bus
286 drive_sys.mem_ctrls = [DriveMemClass(range = r)
287 for r in drive_sys.mem_ranges]
288 for i in xrange(len(drive_sys.mem_ctrls)):
289 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
290
291 drive_sys.init_param = options.init_param
292 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
293elif len(bm) == 1:
294 root = Root(full_system=True, system=test_sys)
295else:
296 print "Error I don't know how to create more than 2 systems."
297 sys.exit(1)
298
299if options.timesync:
300 root.time_sync_enable = True
301
302if options.frame_capture:
303 VncServer.frame_capture = True
304
305Simulation.setWorkCountOptions(test_sys, options)
306Simulation.run(options, root, test_sys, FutureClass)
|