fs.py (9164:d112473185ea) | fs.py (9288:3d6da8559605) |
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1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 108 unchanged lines hidden (view full) --- 117 118test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 119 120if bm[0]: 121 mem_size = bm[0].mem() 122else: 123 mem_size = SysConfig().mem() 124if options.caches or options.l2cache: | 1# Copyright (c) 2010-2012 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 108 unchanged lines hidden (view full) --- 117 118test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)] 119 120if bm[0]: 121 mem_size = bm[0].mem() 122else: 123 mem_size = SysConfig().mem() 124if options.caches or options.l2cache: |
125 test_sys.iocache = IOCache(addr_ranges=[test_sys.physmem.range]) | 125 test_sys.iocache = IOCache(clock = '1GHz', 126 addr_ranges=[test_sys.physmem.range]) |
126 test_sys.iocache.cpu_side = test_sys.iobus.master 127 test_sys.iocache.mem_side = test_sys.membus.slave 128else: 129 test_sys.iobridge = Bridge(delay='50ns', ranges = [test_sys.physmem.range]) 130 test_sys.iobridge.slave = test_sys.iobus.master 131 test_sys.iobridge.master = test_sys.membus.slave 132 133# Sanity check --- 51 unchanged lines hidden --- | 127 test_sys.iocache.cpu_side = test_sys.iobus.master 128 test_sys.iocache.mem_side = test_sys.membus.slave 129else: 130 test_sys.iobridge = Bridge(delay='50ns', ranges = [test_sys.physmem.range]) 131 test_sys.iobridge.slave = test_sys.iobus.master 132 test_sys.iobridge.master = test_sys.membus.slave 133 134# Sanity check --- 51 unchanged lines hidden --- |