fs.py (8920:99083b5b7ed4) | fs.py (8926:570b44fe6e04) |
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1# Copyright (c) 2010-2011 ARM Limited | 1# Copyright (c) 2010-2012 ARM Limited |
2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 118 unchanged lines hidden (view full) --- 128 test_sys.iocache.cpu_side = test_sys.iobus.master 129 test_sys.iocache.mem_side = test_sys.membus.slave 130else: 131 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', 132 ranges = [test_sys.physmem.range]) 133 test_sys.iobridge.slave = test_sys.iobus.master 134 test_sys.iobridge.master = test_sys.membus.slave 135 | 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 118 unchanged lines hidden (view full) --- 128 test_sys.iocache.cpu_side = test_sys.iobus.master 129 test_sys.iocache.mem_side = test_sys.membus.slave 130else: 131 test_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', 132 ranges = [test_sys.physmem.range]) 133 test_sys.iobridge.slave = test_sys.iobus.master 134 test_sys.iobridge.master = test_sys.membus.slave 135 |
136# Sanity check 137if options.fastmem and (options.caches or options.l2cache): 138 fatal("You cannot use fastmem in combination with caches!") 139 |
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136for i in xrange(np): 137 if options.fastmem: | 140for i in xrange(np): 141 if options.fastmem: |
138 test_sys.cpu[i].physmem_port = test_sys.physmem.port | 142 test_sys.cpu[i].fastmem = True |
139 if options.checker: 140 test_sys.cpu[i].addCheckerCpu() 141 142CacheConfig.config_cache(options, test_sys) 143 144if buildEnv['TARGET_ISA'] == 'mips': 145 setMipsOptions(TestCPUClass) 146 --- 8 unchanged lines hidden (view full) --- 155 drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 156 elif buildEnv['TARGET_ISA'] == 'arm': 157 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 158 159 drive_sys.cpu = DriveCPUClass(cpu_id=0) 160 drive_sys.cpu.createInterruptController() 161 drive_sys.cpu.connectAllPorts(drive_sys.membus) 162 if options.fastmem: | 143 if options.checker: 144 test_sys.cpu[i].addCheckerCpu() 145 146CacheConfig.config_cache(options, test_sys) 147 148if buildEnv['TARGET_ISA'] == 'mips': 149 setMipsOptions(TestCPUClass) 150 --- 8 unchanged lines hidden (view full) --- 159 drive_sys = makeX86System(drive_mem_mode, np, bm[1]) 160 elif buildEnv['TARGET_ISA'] == 'arm': 161 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, bm[1]) 162 163 drive_sys.cpu = DriveCPUClass(cpu_id=0) 164 drive_sys.cpu.createInterruptController() 165 drive_sys.cpu.connectAllPorts(drive_sys.membus) 166 if options.fastmem: |
163 drive_sys.cpu.physmem_port = drive_sys.physmem.port | 167 drive_sys.cpu.fastmem = True |
164 if options.kernel is not None: 165 drive_sys.kernel = binary(options.kernel) 166 drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', 167 ranges = [drive_sys.physmem.range]) 168 drive_sys.iobridge.slave = drive_sys.iobus.master 169 drive_sys.iobridge.master = drive_sys.membus.slave 170 171 drive_sys.init_param = options.init_param --- 14 unchanged lines hidden --- | 168 if options.kernel is not None: 169 drive_sys.kernel = binary(options.kernel) 170 drive_sys.iobridge = Bridge(delay='50ns', nack_delay='4ns', 171 ranges = [drive_sys.physmem.range]) 172 drive_sys.iobridge.slave = drive_sys.iobus.master 173 drive_sys.iobridge.master = drive_sys.membus.slave 174 175 drive_sys.init_param = options.init_param --- 14 unchanged lines hidden --- |