fs.py (10056:33db5d81c2cb) | fs.py (10118:5e1f04b4d5e4) |
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1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# | 1# Copyright (c) 2010-2013 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated 10# unmodified and in its entirety in all distributions of the software, 11# modified or unmodified, in source code or in binary form. 12# |
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood 14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc. |
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13# Copyright (c) 2006-2007 The Regents of The University of Michigan 14# All rights reserved. 15# 16# Redistribution and use in source and binary forms, with or without 17# modification, are permitted provided that the following conditions are 18# met: redistributions of source code must retain the above copyright 19# notice, this list of conditions and the following disclaimer; 20# redistributions in binary form must reproduce the above copyright --- 11 unchanged lines hidden (view full) --- 32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 38# 39# Authors: Ali Saidi | 15# Copyright (c) 2006-2007 The Regents of The University of Michigan 16# All rights reserved. 17# 18# Redistribution and use in source and binary forms, with or without 19# modification, are permitted provided that the following conditions are 20# met: redistributions of source code must retain the above copyright 21# notice, this list of conditions and the following disclaimer; 22# redistributions in binary form must reproduce the above copyright --- 11 unchanged lines hidden (view full) --- 34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT 35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE 39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 40# 41# Authors: Ali Saidi |
42# Brad Beckmann |
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40 41import optparse 42import sys 43 44import m5 45from m5.defines import buildEnv 46from m5.objects import * 47from m5.util import addToPath, fatal 48 49addToPath('../common') | 43 44import optparse 45import sys 46 47import m5 48from m5.defines import buildEnv 49from m5.objects import * 50from m5.util import addToPath, fatal 51 52addToPath('../common') |
53addToPath('../ruby') |
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50 | 54 |
55import Ruby 56 |
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51from FSConfig import * 52from SysPaths import * 53from Benchmarks import * 54import Simulation 55import CacheConfig 56import MemConfig 57from Caches import * 58import Options 59 60parser = optparse.OptionParser() 61Options.addCommonOptions(parser) 62Options.addFSOptions(parser) 63 | 57from FSConfig import * 58from SysPaths import * 59from Benchmarks import * 60import Simulation 61import CacheConfig 62import MemConfig 63from Caches import * 64import Options 65 66parser = optparse.OptionParser() 67Options.addCommonOptions(parser) 68Options.addFSOptions(parser) 69 |
70# Add the ruby specific and protocol specific options 71if '--ruby' in sys.argv: 72 Ruby.define_options(parser) 73 |
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64(options, args) = parser.parse_args() 65 66if args: 67 print "Error: script doesn't take any positional arguments" 68 sys.exit(1) 69 70# driver system CPU is always simple... note this is an assignment of 71# a class, not an instance. --- 27 unchanged lines hidden (view full) --- 99 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), 100 SysConfig(disk=options.disk_image, mem=options.mem_size)] 101 else: 102 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 103 104np = options.num_cpus 105 106if buildEnv['TARGET_ISA'] == "alpha": | 74(options, args) = parser.parse_args() 75 76if args: 77 print "Error: script doesn't take any positional arguments" 78 sys.exit(1) 79 80# driver system CPU is always simple... note this is an assignment of 81# a class, not an instance. --- 27 unchanged lines hidden (view full) --- 109 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), 110 SysConfig(disk=options.disk_image, mem=options.mem_size)] 111 else: 112 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)] 113 114np = options.num_cpus 115 116if buildEnv['TARGET_ISA'] == "alpha": |
107 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0]) | 117 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby) |
108elif buildEnv['TARGET_ISA'] == "mips": 109 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 110elif buildEnv['TARGET_ISA'] == "sparc": 111 test_sys = makeSparcSystem(test_mem_mode, bm[0]) 112elif buildEnv['TARGET_ISA'] == "x86": | 118elif buildEnv['TARGET_ISA'] == "mips": 119 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0]) 120elif buildEnv['TARGET_ISA'] == "sparc": 121 test_sys = makeSparcSystem(test_mem_mode, bm[0]) 122elif buildEnv['TARGET_ISA'] == "x86": |
113 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0]) | 123 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0], 124 options.ruby) |
114elif buildEnv['TARGET_ISA'] == "arm": 115 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 116 options.dtb_filename, 117 bare_metal=options.bare_metal) 118 if options.enable_context_switch_stats_dump: 119 test_sys.enable_context_switch_stats_dump = True 120else: 121 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 122 | 125elif buildEnv['TARGET_ISA'] == "arm": 126 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0], 127 options.dtb_filename, 128 bare_metal=options.bare_metal) 129 if options.enable_context_switch_stats_dump: 130 test_sys.enable_context_switch_stats_dump = True 131else: 132 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA']) 133 |
134# Set the cache line size for the entire system 135test_sys.cache_line_size = options.cacheline_size 136 |
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123# Create a top-level voltage domain 124test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 125 126# Create a source clock for the system and set the clock period 127test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 128 voltage_domain = test_sys.voltage_domain) 129 130# Create a CPU voltage domain --- 20 unchanged lines hidden (view full) --- 151 152# For now, assign all the CPUs to the same clock domain 153test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 154 for i in xrange(np)] 155 156if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 157 test_sys.vm = KvmVM() 158 | 137# Create a top-level voltage domain 138test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage) 139 140# Create a source clock for the system and set the clock period 141test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock, 142 voltage_domain = test_sys.voltage_domain) 143 144# Create a CPU voltage domain --- 20 unchanged lines hidden (view full) --- 165 166# For now, assign all the CPUs to the same clock domain 167test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i) 168 for i in xrange(np)] 169 170if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass): 171 test_sys.vm = KvmVM() 172 |
159if options.caches or options.l2cache: 160 # By default the IOCache runs at the system clock 161 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 162 test_sys.iocache.cpu_side = test_sys.iobus.master 163 test_sys.iocache.mem_side = test_sys.membus.slave 164else: 165 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 166 test_sys.iobridge.slave = test_sys.iobus.master 167 test_sys.iobridge.master = test_sys.membus.slave | 173if options.ruby: 174 # Check for timing mode because ruby does not support atomic accesses 175 if not (options.cpu_type == "detailed" or options.cpu_type == "timing"): 176 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!" 177 sys.exit(1) |
168 | 178 |
169# Sanity check 170if options.fastmem: 171 if TestCPUClass != AtomicSimpleCPU: 172 fatal("Fastmem can only be used with atomic CPU!") 173 if (options.caches or options.l2cache): 174 fatal("You cannot use fastmem in combination with caches!") | 179 Ruby.create_system(options, test_sys, test_sys.iobus, test_sys._dma_ports) |
175 | 180 |
176for i in xrange(np): | 181 # Create a seperate clock domain for Ruby 182 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock, 183 voltage_domain = test_sys.voltage_domain) 184 185 for (i, cpu) in enumerate(test_sys.cpu): 186 # 187 # Tie the cpu ports to the correct ruby system ports 188 # 189 cpu.clk_domain = test_sys.cpu_clk_domain 190 cpu.createThreads() 191 cpu.createInterruptController() 192 193 cpu.icache_port = test_sys.ruby._cpu_ruby_ports[i].slave 194 cpu.dcache_port = test_sys.ruby._cpu_ruby_ports[i].slave 195 196 if buildEnv['TARGET_ISA'] == "x86": 197 cpu.itb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave 198 cpu.dtb.walker.port = test_sys.ruby._cpu_ruby_ports[i].slave 199 200 cpu.interrupts.pio = test_sys.ruby._cpu_ruby_ports[i].master 201 cpu.interrupts.int_master = test_sys.ruby._cpu_ruby_ports[i].slave 202 cpu.interrupts.int_slave = test_sys.ruby._cpu_ruby_ports[i].master 203 204 test_sys.ruby._cpu_ruby_ports[i].access_phys_mem = True 205 206 # Create the appropriate memory controllers and connect them to the 207 # PIO bus 208 test_sys.mem_ctrls = [TestMemClass(range = r) for r in test_sys.mem_ranges] 209 for i in xrange(len(test_sys.mem_ctrls)): 210 test_sys.mem_ctrls[i].port = test_sys.iobus.master 211 212else: 213 if options.caches or options.l2cache: 214 # By default the IOCache runs at the system clock 215 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges) 216 test_sys.iocache.cpu_side = test_sys.iobus.master 217 test_sys.iocache.mem_side = test_sys.membus.slave 218 else: 219 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges) 220 test_sys.iobridge.slave = test_sys.iobus.master 221 test_sys.iobridge.master = test_sys.membus.slave 222 223 # Sanity check |
177 if options.fastmem: | 224 if options.fastmem: |
178 test_sys.cpu[i].fastmem = True 179 if options.checker: 180 test_sys.cpu[i].addCheckerCpu() 181 test_sys.cpu[i].createThreads() | 225 if TestCPUClass != AtomicSimpleCPU: 226 fatal("Fastmem can only be used with atomic CPU!") 227 if (options.caches or options.l2cache): 228 fatal("You cannot use fastmem in combination with caches!") |
182 | 229 |
183CacheConfig.config_cache(options, test_sys) 184MemConfig.config_mem(options, test_sys) | 230 for i in xrange(np): 231 if options.fastmem: 232 test_sys.cpu[i].fastmem = True 233 if options.checker: 234 test_sys.cpu[i].addCheckerCpu() 235 test_sys.cpu[i].createThreads() |
185 | 236 |
237 CacheConfig.config_cache(options, test_sys) 238 MemConfig.config_mem(options, test_sys) 239 |
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186if len(bm) == 2: 187 if buildEnv['TARGET_ISA'] == 'alpha': 188 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 189 elif buildEnv['TARGET_ISA'] == 'mips': 190 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 191 elif buildEnv['TARGET_ISA'] == 'sparc': 192 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 193 elif buildEnv['TARGET_ISA'] == 'x86': --- 59 unchanged lines hidden --- | 240if len(bm) == 2: 241 if buildEnv['TARGET_ISA'] == 'alpha': 242 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1]) 243 elif buildEnv['TARGET_ISA'] == 'mips': 244 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1]) 245 elif buildEnv['TARGET_ISA'] == 'sparc': 246 drive_sys = makeSparcSystem(drive_mem_mode, bm[1]) 247 elif buildEnv['TARGET_ISA'] == 'x86': --- 59 unchanged lines hidden --- |