1# Copyright (c) 2010-2013, 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2012-2014 Mark D. Hill and David A. Wood
14# Copyright (c) 2009-2011 Advanced Micro Devices, Inc.
15# Copyright (c) 2006-2007 The Regents of The University of Michigan
16# All rights reserved.
17#
18# Redistribution and use in source and binary forms, with or without
19# modification, are permitted provided that the following conditions are
20# met: redistributions of source code must retain the above copyright
21# notice, this list of conditions and the following disclaimer;
22# redistributions in binary form must reproduce the above copyright
23# notice, this list of conditions and the following disclaimer in the
24# documentation and/or other materials provided with the distribution;
25# neither the name of the copyright holders nor the names of its
26# contributors may be used to endorse or promote products derived from
27# this software without specific prior written permission.
28#
29# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
30# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
31# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
32# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
33# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
34# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
35# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
36# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
37# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
38# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
39# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
40#
41# Authors: Ali Saidi
42# Brad Beckmann
43
44import optparse
45import sys
46
47import m5
48from m5.defines import buildEnv
49from m5.objects import *
50from m5.util import addToPath, fatal
51
52addToPath('../')
53
54from ruby import Ruby
55
56from common.FSConfig import *
57from common.SysPaths import *
58from common.Benchmarks import *
59from common import Simulation
60from common import CacheConfig
61from common import MemConfig
62from common import CpuConfig
63from common.Caches import *
64from common import Options
65
66
67# Check if KVM support has been enabled, we might need to do VM
68# configuration if that's the case.
69have_kvm_support = 'BaseKvmCPU' in globals()
70def is_kvm_cpu(cpu_class):
71 return have_kvm_support and cpu_class != None and \
72 issubclass(cpu_class, BaseKvmCPU)
73
74def cmd_line_template():
75 if options.command_line and options.command_line_file:
76 print "Error: --command-line and --command-line-file are " \
77 "mutually exclusive"
78 sys.exit(1)
79 if options.command_line:
80 return options.command_line
81 if options.command_line_file:
82 return open(options.command_line_file).read().strip()
83 return None
84
85def build_test_system(np):
86 cmdline = cmd_line_template()
87 if buildEnv['TARGET_ISA'] == "alpha":
88 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0], options.ruby,
89 cmdline=cmdline)
90 elif buildEnv['TARGET_ISA'] == "mips":
91 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0], cmdline=cmdline)
92 elif buildEnv['TARGET_ISA'] == "sparc":
93 test_sys = makeSparcSystem(test_mem_mode, bm[0], cmdline=cmdline)
94 elif buildEnv['TARGET_ISA'] == "x86":
95 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0],
96 options.ruby, cmdline=cmdline)
97 elif buildEnv['TARGET_ISA'] == "arm":
98 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
99 options.num_cpus, bm[0], options.dtb_filename,
100 bare_metal=options.bare_metal,
101 cmdline=cmdline,
102 external_memory=options.external_memory_system,
103 ruby=options.ruby)
104 if options.enable_context_switch_stats_dump:
105 test_sys.enable_context_switch_stats_dump = True
106 else:
107 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
108
109 # Set the cache line size for the entire system
110 test_sys.cache_line_size = options.cacheline_size
111
112 # Create a top-level voltage domain
113 test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
114
115 # Create a source clock for the system and set the clock period
116 test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
117 voltage_domain = test_sys.voltage_domain)
118
119 # Create a CPU voltage domain
120 test_sys.cpu_voltage_domain = VoltageDomain()
121
122 # Create a source clock for the CPUs and set the clock period
123 test_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
124 voltage_domain =
125 test_sys.cpu_voltage_domain)
126
127 if options.kernel is not None:
128 test_sys.kernel = binary(options.kernel)
129
130 if options.script is not None:
131 test_sys.readfile = options.script
132
133 if options.lpae:
134 test_sys.have_lpae = True
135
136 if options.virtualisation:
137 test_sys.have_virtualization = True
138
139 test_sys.init_param = options.init_param
140
141 # For now, assign all the CPUs to the same clock domain
142 test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
143 for i in xrange(np)]
144
145 if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
146 test_sys.kvm_vm = KvmVM()
147
148 if options.ruby:
149 # Check for timing mode because ruby does not support atomic accesses
150 if not (options.cpu_type == "DerivO3CPU" or
151 options.cpu_type == "TimingSimpleCPU"):
152 print >> sys.stderr, "Ruby requires TimingSimpleCPU or O3CPU!!"
153 sys.exit(1)
154
155 Ruby.create_system(options, True, test_sys, test_sys.iobus,
156 test_sys._dma_ports)
157
158 # Create a seperate clock domain for Ruby
159 test_sys.ruby.clk_domain = SrcClockDomain(clock = options.ruby_clock,
160 voltage_domain = test_sys.voltage_domain)
161
162 # Connect the ruby io port to the PIO bus,
163 # assuming that there is just one such port.
164 test_sys.iobus.master = test_sys.ruby._io_port.slave
165
166 for (i, cpu) in enumerate(test_sys.cpu):
167 #
168 # Tie the cpu ports to the correct ruby system ports
169 #
170 cpu.clk_domain = test_sys.cpu_clk_domain
171 cpu.createThreads()
172 cpu.createInterruptController()
173
174 cpu.icache_port = test_sys.ruby._cpu_ports[i].slave
175 cpu.dcache_port = test_sys.ruby._cpu_ports[i].slave
176
177 if buildEnv['TARGET_ISA'] in ("x86", "arm"):
178 cpu.itb.walker.port = test_sys.ruby._cpu_ports[i].slave
179 cpu.dtb.walker.port = test_sys.ruby._cpu_ports[i].slave
180
181 if buildEnv['TARGET_ISA'] in "x86":
182 cpu.interrupts[0].pio = test_sys.ruby._cpu_ports[i].master
183 cpu.interrupts[0].int_master = test_sys.ruby._cpu_ports[i].slave
184 cpu.interrupts[0].int_slave = test_sys.ruby._cpu_ports[i].master
185
186 else:
187 if options.caches or options.l2cache:
188 # By default the IOCache runs at the system clock
189 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
190 test_sys.iocache.cpu_side = test_sys.iobus.master
191 test_sys.iocache.mem_side = test_sys.membus.slave
192 elif not options.external_memory_system:
193 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
194 test_sys.iobridge.slave = test_sys.iobus.master
195 test_sys.iobridge.master = test_sys.membus.slave
196
197 # Sanity check
198 if options.fastmem:
199 if TestCPUClass != AtomicSimpleCPU:
200 fatal("Fastmem can only be used with atomic CPU!")
201 if (options.caches or options.l2cache):
202 fatal("You cannot use fastmem in combination with caches!")
203
204 if options.simpoint_profile:
205 if not options.fastmem:
206 # Atomic CPU checked with fastmem option already
207 fatal("SimPoint generation should be done with atomic cpu and fastmem")
208 if np > 1:
209 fatal("SimPoint generation not supported with more than one CPUs")
210
211 for i in xrange(np):
212 if options.fastmem:
213 test_sys.cpu[i].fastmem = True
214 if options.simpoint_profile:
215 test_sys.cpu[i].addSimPointProbe(options.simpoint_interval)
216 if options.checker:
217 test_sys.cpu[i].addCheckerCpu()
218 test_sys.cpu[i].createThreads()
219
220 # If elastic tracing is enabled when not restoring from checkpoint and
221 # when not fast forwarding using the atomic cpu, then check that the
222 # TestCPUClass is DerivO3CPU or inherits from DerivO3CPU. If the check
223 # passes then attach the elastic trace probe.
224 # If restoring from checkpoint or fast forwarding, the code that does this for
225 # FutureCPUClass is in the Simulation module. If the check passes then the
226 # elastic trace probe is attached to the switch CPUs.
227 if options.elastic_trace_en and options.checkpoint_restore == None and \
228 not options.fast_forward:
229 CpuConfig.config_etrace(TestCPUClass, test_sys.cpu, options)
230
231 CacheConfig.config_cache(options, test_sys)
232
233 MemConfig.config_mem(options, test_sys)
234
235 return test_sys
236
237def build_drive_system(np):
238 # driver system CPU is always simple, so is the memory
239 # Note this is an assignment of a class, not an instance.
240 DriveCPUClass = AtomicSimpleCPU
241 drive_mem_mode = 'atomic'
242 DriveMemClass = SimpleMemory
243
244 cmdline = cmd_line_template()
245 if buildEnv['TARGET_ISA'] == 'alpha':
246 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1], cmdline=cmdline)
247 elif buildEnv['TARGET_ISA'] == 'mips':
248 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1], cmdline=cmdline)
249 elif buildEnv['TARGET_ISA'] == 'sparc':
250 drive_sys = makeSparcSystem(drive_mem_mode, bm[1], cmdline=cmdline)
251 elif buildEnv['TARGET_ISA'] == 'x86':
252 drive_sys = makeLinuxX86System(drive_mem_mode, np, bm[1],
253 cmdline=cmdline)
254 elif buildEnv['TARGET_ISA'] == 'arm':
255 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type, np,
256 bm[1], options.dtb_filename, cmdline=cmdline)
257
258 # Create a top-level voltage domain
259 drive_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
260
261 # Create a source clock for the system and set the clock period
262 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
263 voltage_domain = drive_sys.voltage_domain)
264
265 # Create a CPU voltage domain
266 drive_sys.cpu_voltage_domain = VoltageDomain()
267
268 # Create a source clock for the CPUs and set the clock period
269 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock,
270 voltage_domain =
271 drive_sys.cpu_voltage_domain)
272
273 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,
274 cpu_id=0)
275 drive_sys.cpu.createThreads()
276 drive_sys.cpu.createInterruptController()
277 drive_sys.cpu.connectAllPorts(drive_sys.membus)
278 if options.fastmem:
279 drive_sys.cpu.fastmem = True
280 if options.kernel is not None:
281 drive_sys.kernel = binary(options.kernel)
282
283 if is_kvm_cpu(DriveCPUClass):
284 drive_sys.kvm_vm = KvmVM()
285
286 drive_sys.iobridge = Bridge(delay='50ns',
287 ranges = drive_sys.mem_ranges)
288 drive_sys.iobridge.slave = drive_sys.iobus.master
289 drive_sys.iobridge.master = drive_sys.membus.slave
290
291 # Create the appropriate memory controllers and connect them to the
292 # memory bus
293 drive_sys.mem_ctrls = [DriveMemClass(range = r)
294 for r in drive_sys.mem_ranges]
295 for i in xrange(len(drive_sys.mem_ctrls)):
296 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
297
298 drive_sys.init_param = options.init_param
299
300 return drive_sys
301
302# Add options
303parser = optparse.OptionParser()
304Options.addCommonOptions(parser)
305Options.addFSOptions(parser)
306
307# Add the ruby specific and protocol specific options
308if '--ruby' in sys.argv:
309 Ruby.define_options(parser)
310
311(options, args) = parser.parse_args()
312
313if args:
314 print "Error: script doesn't take any positional arguments"
315 sys.exit(1)
316
317# system under test can be any CPU
318(TestCPUClass, test_mem_mode, FutureClass) = Simulation.setCPUClass(options)
319
320# Match the memories with the CPUs, based on the options for the test system
321TestMemClass = Simulation.setMemClass(options)
322
323if options.benchmark:
324 try:
325 bm = Benchmarks[options.benchmark]
326 except KeyError:
327 print "Error benchmark %s has not been defined." % options.benchmark
328 print "Valid benchmarks are: %s" % DefinedBenchmarks
329 sys.exit(1)
330else:
331 if options.dual:
332 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
333 mem=options.mem_size, os_type=options.os_type),
334 SysConfig(disk=options.disk_image, rootdev=options.root_device,
335 mem=options.mem_size, os_type=options.os_type)]
336 else:
337 bm = [SysConfig(disk=options.disk_image, rootdev=options.root_device,
338 mem=options.mem_size, os_type=options.os_type)]
339
340np = options.num_cpus
341
342test_sys = build_test_system(np)
343if len(bm) == 2:
344 drive_sys = build_drive_system(np)
345 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
346elif len(bm) == 1 and options.dist:
347 # This system is part of a dist-gem5 simulation
348 root = makeDistRoot(test_sys,
349 options.dist_rank,
350 options.dist_size,
351 options.dist_server_name,
352 options.dist_server_port,
353 options.dist_sync_repeat,
354 options.dist_sync_start,
355 options.ethernet_linkspeed,
356 options.ethernet_linkdelay,
357 options.etherdump);
358elif len(bm) == 1:
359 root = Root(full_system=True, system=test_sys)
360else:
361 print "Error I don't know how to create more than 2 systems."
362 sys.exit(1)
363
364if options.timesync:
365 root.time_sync_enable = True
366
367if options.frame_capture:
368 VncServer.frame_capture = True
369
370Simulation.setWorkCountOptions(test_sys, options)
371Simulation.run(options, root, test_sys, FutureClass)