1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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169 if options.checker:
170 test_sys.cpu[i].addCheckerCpu()
171 test_sys.cpu[i].createThreads()
172
173CacheConfig.config_cache(options, test_sys)
174
175# Create the appropriate memory controllers and connect them to the
176# memory bus
177test_sys.mem_ctrls = [TestMemClass(range = r, conf_table_reported = True)
178 for r in test_sys.mem_ranges]
179for i in xrange(len(test_sys.mem_ctrls)):
180 test_sys.mem_ctrls[i].port = test_sys.membus.master
181
182if len(bm) == 2:
183 if buildEnv['TARGET_ISA'] == 'alpha':
184 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
185 elif buildEnv['TARGET_ISA'] == 'mips':
186 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])

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220
221 drive_sys.iobridge = Bridge(delay='50ns',
222 ranges = drive_sys.mem_ranges)
223 drive_sys.iobridge.slave = drive_sys.iobus.master
224 drive_sys.iobridge.master = drive_sys.membus.slave
225
226 # Create the appropriate memory controllers and connect them to the
227 # memory bus
228 drive_sys.mem_ctrls = [DriveMemClass(range = r, conf_table_reported = True)
229 for r in drive_sys.mem_ranges]
230 for i in xrange(len(drive_sys.mem_ctrls)):
231 drive_sys.mem_ctrls[i].port = drive_sys.membus.master
232
233 drive_sys.init_param = options.init_param
234 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
235elif len(bm) == 1:
236 root = Root(full_system=True, system=test_sys)

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