1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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97 if options.dual:
98 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size), SysConfig(disk=options.disk_image, mem=options.mem_size)]
99 else:
100 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
101
102np = options.num_cpus
103
104if buildEnv['TARGET_ISA'] == "alpha":
105 test_sys = makeLinuxAlphaSystem(test_mem_mode, TestMemClass, bm[0])
106elif buildEnv['TARGET_ISA'] == "mips":
107 test_sys = makeLinuxMipsSystem(test_mem_mode, TestMemClass, bm[0])
108elif buildEnv['TARGET_ISA'] == "sparc":
109 test_sys = makeSparcSystem(test_mem_mode, TestMemClass, bm[0])
110elif buildEnv['TARGET_ISA'] == "x86":
111 test_sys = makeLinuxX86System(test_mem_mode, TestMemClass,
112 options.num_cpus, bm[0])
113elif buildEnv['TARGET_ISA'] == "arm":
114 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
115 TestMemClass, bm[0], options.dtb_filename,
116 bare_metal=options.bare_metal)
117else:
118 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
119
120# Create a source clock for the system and set the clock period
121test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
122
123# Create a source clock for the CPUs and set the clock period

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159 if options.fastmem:
160 test_sys.cpu[i].fastmem = True
161 if options.checker:
162 test_sys.cpu[i].addCheckerCpu()
163 test_sys.cpu[i].createThreads()
164
165CacheConfig.config_cache(options, test_sys)
166
167if len(bm) == 2:
168 if buildEnv['TARGET_ISA'] == 'alpha':
169 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, DriveMemClass, bm[1])
170 elif buildEnv['TARGET_ISA'] == 'mips':
171 drive_sys = makeLinuxMipsSystem(drive_mem_mode, DriveMemClass, bm[1])
172 elif buildEnv['TARGET_ISA'] == 'sparc':
173 drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1])
174 elif buildEnv['TARGET_ISA'] == 'x86':
175 drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1])
176 elif buildEnv['TARGET_ISA'] == 'arm':
177 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
178 DriveMemClass, bm[1])
179
180 # Create a source clock for the system and set the clock period
181 drive_sys.clk_domain = SrcClockDomain(clock = options.sys_clock)
182
183 # Create a source clock for the CPUs and set the clock period
184 drive_sys.cpu_clk_domain = SrcClockDomain(clock = options.cpu_clock)
185
186 drive_sys.cpu = DriveCPUClass(clk_domain=drive_sys.cpu_clk_domain,

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196 if is_kvm_cpu(DriveCPUClass):
197 drive_sys.vm = KvmVM()
198
199 drive_sys.iobridge = Bridge(delay='50ns',
200 ranges = drive_sys.mem_ranges)
201 drive_sys.iobridge.slave = drive_sys.iobus.master
202 drive_sys.iobridge.master = drive_sys.membus.slave
203
204 drive_sys.init_param = options.init_param
205 root = makeDualRoot(True, test_sys, drive_sys, options.etherdump)
206elif len(bm) == 1:
207 root = Root(full_system=True, system=test_sys)
208else:
209 print "Error I don't know how to create more than 2 systems."
210 sys.exit(1)
211
212if options.timesync:
213 root.time_sync_enable = True
214
215if options.frame_capture:
216 VncServer.frame_capture = True
217
218Simulation.setWorkCountOptions(test_sys, options)
219Simulation.run(options, root, test_sys, FutureClass)