1# Copyright (c) 2006-2007 The Regents of The University of Michigan
2# All rights reserved.
3#
4# Redistribution and use in source and binary forms, with or without
5# modification, are permitted provided that the following conditions are
6# met: redistributions of source code must retain the above copyright
7# notice, this list of conditions and the following disclaimer;
8# redistributions in binary form must reproduce the above copyright

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116 test_sys.l2.cpu_side = test_sys.tol2bus.port
117 test_sys.l2.mem_side = test_sys.membus.port
118
119test_sys.cpu = [TestCPUClass(cpu_id=i) for i in xrange(np)]
120for i in xrange(np):
121 if options.caches:
122 test_sys.cpu[i].addPrivateSplitL1Caches(L1Cache(size = '32kB'),
123 L1Cache(size = '64kB'))
124
125 if options.l2cache:
126 test_sys.cpu[i].connectMemPorts(test_sys.tol2bus)
127 else:
128 test_sys.cpu[i].connectMemPorts(test_sys.membus)
129
130if len(bm) == 2:
131 if m5.build_env['TARGET_ISA'] == 'alpha':
132 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])

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