1# Copyright (c) 2010-2013 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Copyright (c) 2006-2007 The Regents of The University of Michigan
14# All rights reserved.
15#
16# Redistribution and use in source and binary forms, with or without
17# modification, are permitted provided that the following conditions are
18# met: redistributions of source code must retain the above copyright
19# notice, this list of conditions and the following disclaimer;
20# redistributions in binary form must reproduce the above copyright

--- 11 unchanged lines hidden (view full) ---

32# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
33# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
34# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
35# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
36# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
37# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38#
39# Authors: Ali Saidi
40
41import optparse
42import sys
43
44import m5
45from m5.defines import buildEnv
46from m5.objects import *
47from m5.util import addToPath, fatal
48
49addToPath('../common')
50
51from FSConfig import *
52from SysPaths import *
53from Benchmarks import *
54import Simulation
55import CacheConfig
56import MemConfig
57from Caches import *
58import Options
59
60parser = optparse.OptionParser()
61Options.addCommonOptions(parser)
62Options.addFSOptions(parser)
63
64(options, args) = parser.parse_args()
65
66if args:
67 print "Error: script doesn't take any positional arguments"
68 sys.exit(1)
69
70# driver system CPU is always simple... note this is an assignment of
71# a class, not an instance.

--- 27 unchanged lines hidden (view full) ---

99 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size),
100 SysConfig(disk=options.disk_image, mem=options.mem_size)]
101 else:
102 bm = [SysConfig(disk=options.disk_image, mem=options.mem_size)]
103
104np = options.num_cpus
105
106if buildEnv['TARGET_ISA'] == "alpha":
107 test_sys = makeLinuxAlphaSystem(test_mem_mode, bm[0])
108elif buildEnv['TARGET_ISA'] == "mips":
109 test_sys = makeLinuxMipsSystem(test_mem_mode, bm[0])
110elif buildEnv['TARGET_ISA'] == "sparc":
111 test_sys = makeSparcSystem(test_mem_mode, bm[0])
112elif buildEnv['TARGET_ISA'] == "x86":
113 test_sys = makeLinuxX86System(test_mem_mode, options.num_cpus, bm[0])
114elif buildEnv['TARGET_ISA'] == "arm":
115 test_sys = makeArmSystem(test_mem_mode, options.machine_type, bm[0],
116 options.dtb_filename,
117 bare_metal=options.bare_metal)
118 if options.enable_context_switch_stats_dump:
119 test_sys.enable_context_switch_stats_dump = True
120else:
121 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
122
123# Create a top-level voltage domain
124test_sys.voltage_domain = VoltageDomain(voltage = options.sys_voltage)
125
126# Create a source clock for the system and set the clock period
127test_sys.clk_domain = SrcClockDomain(clock = options.sys_clock,
128 voltage_domain = test_sys.voltage_domain)
129
130# Create a CPU voltage domain

--- 20 unchanged lines hidden (view full) ---

151
152# For now, assign all the CPUs to the same clock domain
153test_sys.cpu = [TestCPUClass(clk_domain=test_sys.cpu_clk_domain, cpu_id=i)
154 for i in xrange(np)]
155
156if is_kvm_cpu(TestCPUClass) or is_kvm_cpu(FutureClass):
157 test_sys.vm = KvmVM()
158
159if options.caches or options.l2cache:
160 # By default the IOCache runs at the system clock
161 test_sys.iocache = IOCache(addr_ranges = test_sys.mem_ranges)
162 test_sys.iocache.cpu_side = test_sys.iobus.master
163 test_sys.iocache.mem_side = test_sys.membus.slave
164else:
165 test_sys.iobridge = Bridge(delay='50ns', ranges = test_sys.mem_ranges)
166 test_sys.iobridge.slave = test_sys.iobus.master
167 test_sys.iobridge.master = test_sys.membus.slave
168
169# Sanity check
170if options.fastmem:
171 if TestCPUClass != AtomicSimpleCPU:
172 fatal("Fastmem can only be used with atomic CPU!")
173 if (options.caches or options.l2cache):
174 fatal("You cannot use fastmem in combination with caches!")
175
176for i in xrange(np):
177 if options.fastmem:
178 test_sys.cpu[i].fastmem = True
179 if options.checker:
180 test_sys.cpu[i].addCheckerCpu()
181 test_sys.cpu[i].createThreads()
182
183CacheConfig.config_cache(options, test_sys)
184MemConfig.config_mem(options, test_sys)
185
186if len(bm) == 2:
187 if buildEnv['TARGET_ISA'] == 'alpha':
188 drive_sys = makeLinuxAlphaSystem(drive_mem_mode, bm[1])
189 elif buildEnv['TARGET_ISA'] == 'mips':
190 drive_sys = makeLinuxMipsSystem(drive_mem_mode, bm[1])
191 elif buildEnv['TARGET_ISA'] == 'sparc':
192 drive_sys = makeSparcSystem(drive_mem_mode, bm[1])
193 elif buildEnv['TARGET_ISA'] == 'x86':

--- 59 unchanged lines hidden ---