1# Copyright (c) 2010-2012 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

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115 options.num_cpus, bm[0])
116elif buildEnv['TARGET_ISA'] == "arm":
117 test_sys = makeArmSystem(test_mem_mode, options.machine_type,
118 TestMemClass, bm[0], options.dtb_filename,
119 bare_metal=options.bare_metal)
120else:
121 fatal("Incapable of building %s full system!", buildEnv['TARGET_ISA'])
122
123test_sys.clock = options.sys_clock
124
125if options.kernel is not None:
126 test_sys.kernel = binary(options.kernel)
127
128if options.script is not None:
129 test_sys.readfile = options.script
130
131test_sys.init_param = options.init_param
132

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169 elif buildEnv['TARGET_ISA'] == 'sparc':
170 drive_sys = makeSparcSystem(drive_mem_mode, DriveMemClass, bm[1])
171 elif buildEnv['TARGET_ISA'] == 'x86':
172 drive_sys = makeX86System(drive_mem_mode, DriveMemClass, np, bm[1])
173 elif buildEnv['TARGET_ISA'] == 'arm':
174 drive_sys = makeArmSystem(drive_mem_mode, options.machine_type,
175 DriveMemClass, bm[1])
176
177 drive_sys.clock = options.sys_clock
178
179 drive_sys.cpu = DriveCPUClass(cpu_id=0)
180 drive_sys.cpu.createThreads()
181 drive_sys.cpu.createInterruptController()
182 drive_sys.cpu.connectAllPorts(drive_sys.membus)
183 if options.fastmem:
184 drive_sys.cpu.fastmem = True
185 if options.kernel is not None:
186 drive_sys.kernel = binary(options.kernel)

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