fs_bigLITTLE.py (12097:77a3d2890ba6) fs_bigLITTLE.py (12153:dc6e9f6dfd9c)
1# Copyright (c) 2016-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 101 unchanged lines hidden (view full) ---

110 cpu_config = [ CpuConfig.get("ex5_LITTLE"), ex5_LITTLE.L1I,
111 ex5_LITTLE.L1D, ex5_LITTLE.WalkCache, ex5_LITTLE.L2 ]
112 super(Ex5LittleCluster, self).__init__(system, num_cpus, cpu_clock,
113 cpu_voltage, *cpu_config)
114
115def createSystem(caches, kernel, bootscript, disks=[]):
116 sys = devices.SimpleSystem(caches, default_mem_size,
117 kernel=SysPaths.binary(kernel),
1# Copyright (c) 2016-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license

--- 101 unchanged lines hidden (view full) ---

110 cpu_config = [ CpuConfig.get("ex5_LITTLE"), ex5_LITTLE.L1I,
111 ex5_LITTLE.L1D, ex5_LITTLE.WalkCache, ex5_LITTLE.L2 ]
112 super(Ex5LittleCluster, self).__init__(system, num_cpus, cpu_clock,
113 cpu_voltage, *cpu_config)
114
115def createSystem(caches, kernel, bootscript, disks=[]):
116 sys = devices.SimpleSystem(caches, default_mem_size,
117 kernel=SysPaths.binary(kernel),
118 readfile=bootscript,
119 machine_type="DTOnly")
118 readfile=bootscript)
120
121 sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
122 sys.mem_ctrls.port = sys.membus.master
123
124 sys.connect()
125
126 # Attach disk images
127 if disks:

--- 199 unchanged lines hidden --- 		119
120 sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
121 sys.mem_ctrls.port = sys.membus.master
122
123 sys.connect()
124
125 # Attach disk images
126 if disks:

--- 199 unchanged lines hidden ---