1# Copyright (c) 2016-2017 ARM Limited |
2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license 9# terms below provided that you ensure that this notice is replicated --- 194 unchanged lines hidden (view full) --- 204 m5.util.panic("Little CPU model requires caches") 205 206 # Linux device tree 207 system.dtb_filename = SysPaths.binary(options.dtb) 208 209 return root 210 211 |
212def instantiate(options, checkpoint_dir=None): |
213 # Get and load from the chkpt or simpoint checkpoint |
214 if options.restore_from: 215 if checkpoint_dir and not os.path.isabs(options.restore_from): 216 cpt = os.path.join(checkpoint_dir, options.restore_from) 217 else: 218 cpt = options.restore_from 219 220 m5.util.inform("Restoring from checkpoint %s", cpt) 221 m5.instantiate(cpt) |
222 else: 223 m5.instantiate() 224 225 226def run(checkpoint_dir=m5.options.outdir): 227 # start simulation (and drop checkpoints when requested) 228 while True: 229 event = m5.simulate() --- 11 unchanged lines hidden (view full) --- 241 242 243def main(): 244 parser = argparse.ArgumentParser( 245 description="Generic ARM big.LITTLE configuration") 246 addOptions(parser) 247 options = parser.parse_args() 248 root = build(options) |
249 instantiate(options) |
250 run() 251 252 253if __name__ == "__m5_main__": 254 main() |