1# Copyright (c) 2016 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 94 unchanged lines hidden (view full) --- 103 for dev in sys.pci_vio_block: 104 sys.attach_pci(dev) 105 106 sys.realview.setupBootLoader(sys.membus, sys, SysPaths.binary) 107 108 return sys 109 110 |
111def addOptions(parser): |
112 parser.add_argument("--restore-from", type=str, default=None, 113 help="Restore from checkpoint") 114 parser.add_argument("--dtb", type=str, default=default_dtb, 115 help="DTB file to load") 116 parser.add_argument("--kernel", type=str, default=default_kernel, 117 help="Linux kernel") 118 parser.add_argument("--disk", action="append", type=str, default=[], 119 help="Disks to instantiate") --- 10 unchanged lines hidden (view full) --- 130 parser.add_argument("--caches", action="store_true", default=False, 131 help="Instantiate caches") 132 parser.add_argument("--last-cache-level", type=int, default=2, 133 help="Last level of caches (e.g. 3 for L3)") 134 parser.add_argument("--big-cpu-clock", type=str, default="2GHz", 135 help="Big CPU clock frequency") 136 parser.add_argument("--little-cpu-clock", type=str, default="1GHz", 137 help="Little CPU clock frequency") |
138 return parser |
139 |
140 141def build(options): |
142 m5.ticks.fixGlobalFrequency() 143 |
144 kernel_cmd = [ 145 "earlyprintk=pl011,0x1c090000", 146 "console=ttyAMA0", 147 "lpj=19988480", 148 "norandmaps", 149 "loglevel=8", 150 "mem=%s" % default_mem_size, 151 "root=/dev/vda1", --- 49 unchanged lines hidden (view full) --- 201 if options.big_cpus > 0 and system.bigCluster.requireCaches(): 202 m5.util.panic("Big CPU model requires caches") 203 if options.little_cpus > 0 and system.littleCluster.requireCaches(): 204 m5.util.panic("Little CPU model requires caches") 205 206 # Linux device tree 207 system.dtb_filename = SysPaths.binary(options.dtb) 208 |
209 return root 210 211 212def instantiate(checkpoint_path=None): |
213 # Get and load from the chkpt or simpoint checkpoint |
214 if checkpoint_path is not None: 215 m5.util.inform("Restoring from checkpoint %s", checkpoint_path) 216 m5.instantiate(checkpoint_path) |
217 else: 218 m5.instantiate() 219 |
220 221def run(checkpoint_dir=m5.options.outdir): |
222 # start simulation (and drop checkpoints when requested) 223 while True: 224 event = m5.simulate() 225 exit_msg = event.getCause() 226 if exit_msg == "checkpoint": 227 print "Dropping checkpoint at tick %d" % m5.curTick() |
228 cpt_dir = os.path.join(checkpoint_dir, "cpt.%d" % m5.curTick()) 229 m5.checkpoint(cpt_dir) |
230 print "Checkpoint done." 231 else: 232 print exit_msg, " @ ", m5.curTick() 233 break 234 235 sys.exit(event.getCode()) 236 237 |
238def main(): 239 parser = argparse.ArgumentParser( 240 description="Generic ARM big.LITTLE configuration") 241 addOptions(parser) 242 options = parser.parse_args() 243 root = build(options) 244 instantiate(options.restore_from) 245 run() 246 247 |
248if __name__ == "__m5_main__": 249 main() |