1# Copyright (c) 2016-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Gabor Dozsa
37# Andreas Sandberg
38
39# This is an example configuration script for full system simulation of
40# a generic ARM bigLITTLE system.
41
42
43import argparse
44import os
45import sys
46import m5
47import m5.util
48from m5.objects import *
49
50m5.util.addToPath("../../")
51
52from common import SysPaths
53from common import CpuConfig
54from common.cores.arm import ex5_big, ex5_LITTLE
55
56import devices
57from devices import AtomicCluster, KvmCluster
58
59
60default_dtb = 'armv8_gem5_v1_big_little_2_2.dtb'
61default_kernel = 'vmlinux4.3.aarch64'
62default_disk = 'aarch64-ubuntu-trusty-headless.img'
63default_rcs = 'bootscript.rcS'
64
65default_mem_size= "2GB"
66
67def _to_ticks(value):
68 """Helper function to convert a latency from string format to Ticks"""
69
70 return m5.ticks.fromSeconds(m5.util.convert.anyToLatency(value))
71
72def _using_pdes(root):
73 """Determine if the simulator is using multiple parallel event queues"""
74
75 for obj in root.descendants():
76 if not m5.proxy.isproxy(obj.eventq_index) and \
77 obj.eventq_index != root.eventq_index:
78 return True
79
80 return False
81
82
83class BigCluster(devices.CpuCluster):
84 def __init__(self, system, num_cpus, cpu_clock,
85 cpu_voltage="1.0V"):
86 cpu_config = [ CpuConfig.get("O3_ARM_v7a_3"), devices.L1I, devices.L1D,
87 devices.WalkCache, devices.L2 ]
88 super(BigCluster, self).__init__(system, num_cpus, cpu_clock,
89 cpu_voltage, *cpu_config)
90
91class LittleCluster(devices.CpuCluster):
92 def __init__(self, system, num_cpus, cpu_clock,
93 cpu_voltage="1.0V"):
94 cpu_config = [ CpuConfig.get("MinorCPU"), devices.L1I, devices.L1D,
95 devices.WalkCache, devices.L2 ]
96 super(LittleCluster, self).__init__(system, num_cpus, cpu_clock,
97 cpu_voltage, *cpu_config)
98
99class Ex5BigCluster(devices.CpuCluster):
100 def __init__(self, system, num_cpus, cpu_clock,
101 cpu_voltage="1.0V"):
102 cpu_config = [ CpuConfig.get("ex5_big"), ex5_big.L1I, ex5_big.L1D,
103 ex5_big.WalkCache, ex5_big.L2 ]
104 super(Ex5BigCluster, self).__init__(system, num_cpus, cpu_clock,
105 cpu_voltage, *cpu_config)
106
107class Ex5LittleCluster(devices.CpuCluster):
108 def __init__(self, system, num_cpus, cpu_clock,
109 cpu_voltage="1.0V"):
110 cpu_config = [ CpuConfig.get("ex5_LITTLE"), ex5_LITTLE.L1I,
111 ex5_LITTLE.L1D, ex5_LITTLE.WalkCache, ex5_LITTLE.L2 ]
112 super(Ex5LittleCluster, self).__init__(system, num_cpus, cpu_clock,
113 cpu_voltage, *cpu_config)
114
115def createSystem(caches, kernel, bootscript, disks=[]):
116 sys = devices.SimpleSystem(caches, default_mem_size,
117 kernel=SysPaths.binary(kernel),
| 1# Copyright (c) 2016-2017 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated
10# unmodified and in its entirety in all distributions of the software,
11# modified or unmodified, in source code or in binary form.
12#
13# Redistribution and use in source and binary forms, with or without
14# modification, are permitted provided that the following conditions are
15# met: redistributions of source code must retain the above copyright
16# notice, this list of conditions and the following disclaimer;
17# redistributions in binary form must reproduce the above copyright
18# notice, this list of conditions and the following disclaimer in the
19# documentation and/or other materials provided with the distribution;
20# neither the name of the copyright holders nor the names of its
21# contributors may be used to endorse or promote products derived from
22# this software without specific prior written permission.
23#
24# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
25# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
26# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
27# A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
28# OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
29# SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
30# LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
31# DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
32# THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
33# (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
34# OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
35#
36# Authors: Gabor Dozsa
37# Andreas Sandberg
38
39# This is an example configuration script for full system simulation of
40# a generic ARM bigLITTLE system.
41
42
43import argparse
44import os
45import sys
46import m5
47import m5.util
48from m5.objects import *
49
50m5.util.addToPath("../../")
51
52from common import SysPaths
53from common import CpuConfig
54from common.cores.arm import ex5_big, ex5_LITTLE
55
56import devices
57from devices import AtomicCluster, KvmCluster
58
59
60default_dtb = 'armv8_gem5_v1_big_little_2_2.dtb'
61default_kernel = 'vmlinux4.3.aarch64'
62default_disk = 'aarch64-ubuntu-trusty-headless.img'
63default_rcs = 'bootscript.rcS'
64
65default_mem_size= "2GB"
66
67def _to_ticks(value):
68 """Helper function to convert a latency from string format to Ticks"""
69
70 return m5.ticks.fromSeconds(m5.util.convert.anyToLatency(value))
71
72def _using_pdes(root):
73 """Determine if the simulator is using multiple parallel event queues"""
74
75 for obj in root.descendants():
76 if not m5.proxy.isproxy(obj.eventq_index) and \
77 obj.eventq_index != root.eventq_index:
78 return True
79
80 return False
81
82
83class BigCluster(devices.CpuCluster):
84 def __init__(self, system, num_cpus, cpu_clock,
85 cpu_voltage="1.0V"):
86 cpu_config = [ CpuConfig.get("O3_ARM_v7a_3"), devices.L1I, devices.L1D,
87 devices.WalkCache, devices.L2 ]
88 super(BigCluster, self).__init__(system, num_cpus, cpu_clock,
89 cpu_voltage, *cpu_config)
90
91class LittleCluster(devices.CpuCluster):
92 def __init__(self, system, num_cpus, cpu_clock,
93 cpu_voltage="1.0V"):
94 cpu_config = [ CpuConfig.get("MinorCPU"), devices.L1I, devices.L1D,
95 devices.WalkCache, devices.L2 ]
96 super(LittleCluster, self).__init__(system, num_cpus, cpu_clock,
97 cpu_voltage, *cpu_config)
98
99class Ex5BigCluster(devices.CpuCluster):
100 def __init__(self, system, num_cpus, cpu_clock,
101 cpu_voltage="1.0V"):
102 cpu_config = [ CpuConfig.get("ex5_big"), ex5_big.L1I, ex5_big.L1D,
103 ex5_big.WalkCache, ex5_big.L2 ]
104 super(Ex5BigCluster, self).__init__(system, num_cpus, cpu_clock,
105 cpu_voltage, *cpu_config)
106
107class Ex5LittleCluster(devices.CpuCluster):
108 def __init__(self, system, num_cpus, cpu_clock,
109 cpu_voltage="1.0V"):
110 cpu_config = [ CpuConfig.get("ex5_LITTLE"), ex5_LITTLE.L1I,
111 ex5_LITTLE.L1D, ex5_LITTLE.WalkCache, ex5_LITTLE.L2 ]
112 super(Ex5LittleCluster, self).__init__(system, num_cpus, cpu_clock,
113 cpu_voltage, *cpu_config)
114
115def createSystem(caches, kernel, bootscript, disks=[]):
116 sys = devices.SimpleSystem(caches, default_mem_size,
117 kernel=SysPaths.binary(kernel),
|
120
121 sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
122 sys.mem_ctrls.port = sys.membus.master
123
124 sys.connect()
125
126 # Attach disk images
127 if disks:
128 def cow_disk(image_file):
129 image = CowDiskImage()
130 image.child.image_file = SysPaths.disk(image_file)
131 return image
132
133 sys.disk_images = [ cow_disk(f) for f in disks ]
134 sys.pci_vio_block = [ PciVirtIO(vio=VirtIOBlock(image=img))
135 for img in sys.disk_images ]
136 for dev in sys.pci_vio_block:
137 sys.attach_pci(dev)
138
139 sys.realview.setupBootLoader(sys.membus, sys, SysPaths.binary)
140
141 return sys
142
143cpu_types = {
144 "atomic" : (AtomicCluster, AtomicCluster),
145 "timing" : (BigCluster, LittleCluster),
146 "exynos" : (Ex5BigCluster, Ex5LittleCluster),
147}
148
149# Only add the KVM CPU if it has been compiled into gem5
150if devices.have_kvm:
151 cpu_types["kvm"] = (KvmCluster, KvmCluster)
152
153
154def addOptions(parser):
155 parser.add_argument("--restore-from", type=str, default=None,
156 help="Restore from checkpoint")
157 parser.add_argument("--dtb", type=str, default=default_dtb,
158 help="DTB file to load")
159 parser.add_argument("--kernel", type=str, default=default_kernel,
160 help="Linux kernel")
161 parser.add_argument("--disk", action="append", type=str, default=[],
162 help="Disks to instantiate")
163 parser.add_argument("--bootscript", type=str, default=default_rcs,
164 help="Linux bootscript")
165 parser.add_argument("--cpu-type", type=str, choices=cpu_types.keys(),
166 default="timing",
167 help="CPU simulation mode. Default: %(default)s")
168 parser.add_argument("--kernel-init", type=str, default="/sbin/init",
169 help="Override init")
170 parser.add_argument("--big-cpus", type=int, default=1,
171 help="Number of big CPUs to instantiate")
172 parser.add_argument("--little-cpus", type=int, default=1,
173 help="Number of little CPUs to instantiate")
174 parser.add_argument("--caches", action="store_true", default=False,
175 help="Instantiate caches")
176 parser.add_argument("--last-cache-level", type=int, default=2,
177 help="Last level of caches (e.g. 3 for L3)")
178 parser.add_argument("--big-cpu-clock", type=str, default="2GHz",
179 help="Big CPU clock frequency")
180 parser.add_argument("--little-cpu-clock", type=str, default="1GHz",
181 help="Little CPU clock frequency")
182 parser.add_argument("--sim-quantum", type=str, default="1ms",
183 help="Simulation quantum for parallel simulation. " \
184 "Default: %(default)s")
185 return parser
186
187def build(options):
188 m5.ticks.fixGlobalFrequency()
189
190 kernel_cmd = [
191 "earlyprintk=pl011,0x1c090000",
192 "console=ttyAMA0",
193 "lpj=19988480",
194 "norandmaps",
195 "loglevel=8",
196 "mem=%s" % default_mem_size,
197 "root=/dev/vda1",
198 "rw",
199 "init=%s" % options.kernel_init,
200 "vmalloc=768MB",
201 ]
202
203 root = Root(full_system=True)
204
205 disks = [default_disk] if len(options.disk) == 0 else options.disk
206 system = createSystem(options.caches,
207 options.kernel,
208 options.bootscript,
209 disks=disks)
210
211 root.system = system
212 system.boot_osflags = " ".join(kernel_cmd)
213
214 if options.big_cpus + options.little_cpus == 0:
215 m5.util.panic("Empty CPU clusters")
216
217 big_model, little_model = cpu_types[options.cpu_type]
218
219 all_cpus = []
220 # big cluster
221 if options.big_cpus > 0:
222 system.bigCluster = big_model(system, options.big_cpus,
223 options.big_cpu_clock)
224 system.mem_mode = system.bigCluster.memoryMode()
225 all_cpus += system.bigCluster.cpus
226
227 # little cluster
228 if options.little_cpus > 0:
229 system.littleCluster = little_model(system, options.little_cpus,
230 options.little_cpu_clock)
231 system.mem_mode = system.littleCluster.memoryMode()
232 all_cpus += system.littleCluster.cpus
233
234 # Figure out the memory mode
235 if options.big_cpus > 0 and options.little_cpus > 0 and \
236 system.littleCluster.memoryMode() != system.littleCluster.memoryMode():
237 m5.util.panic("Memory mode missmatch among CPU clusters")
238
239
240 # create caches
241 system.addCaches(options.caches, options.last_cache_level)
242 if not options.caches:
243 if options.big_cpus > 0 and system.bigCluster.requireCaches():
244 m5.util.panic("Big CPU model requires caches")
245 if options.little_cpus > 0 and system.littleCluster.requireCaches():
246 m5.util.panic("Little CPU model requires caches")
247
248 # Create a KVM VM and do KVM-specific configuration
249 if issubclass(big_model, KvmCluster):
250 _build_kvm(system, all_cpus)
251
252 # Linux device tree
253 system.dtb_filename = SysPaths.binary(options.dtb)
254
255 return root
256
257def _build_kvm(system, cpus):
258 system.kvm_vm = KvmVM()
259
260 # Assign KVM CPUs to their own event queues / threads. This
261 # has to be done after creating caches and other child objects
262 # since these mustn't inherit the CPU event queue.
263 if len(cpus) > 1:
264 device_eq = 0
265 first_cpu_eq = 1
266 for idx, cpu in enumerate(cpus):
267 # Child objects usually inherit the parent's event
268 # queue. Override that and use the same event queue for
269 # all devices.
270 for obj in cpu.descendants():
271 obj.eventq_index = device_eq
272 cpu.eventq_index = first_cpu_eq + idx
273
274
275
276def instantiate(options, checkpoint_dir=None):
277 # Setup the simulation quantum if we are running in PDES-mode
278 # (e.g., when using KVM)
279 root = Root.getInstance()
280 if root and _using_pdes(root):
281 m5.util.inform("Running in PDES mode with a %s simulation quantum.",
282 options.sim_quantum)
283 root.sim_quantum = _to_ticks(options.sim_quantum)
284
285 # Get and load from the chkpt or simpoint checkpoint
286 if options.restore_from:
287 if checkpoint_dir and not os.path.isabs(options.restore_from):
288 cpt = os.path.join(checkpoint_dir, options.restore_from)
289 else:
290 cpt = options.restore_from
291
292 m5.util.inform("Restoring from checkpoint %s", cpt)
293 m5.instantiate(cpt)
294 else:
295 m5.instantiate()
296
297
298def run(checkpoint_dir=m5.options.outdir):
299 # start simulation (and drop checkpoints when requested)
300 while True:
301 event = m5.simulate()
302 exit_msg = event.getCause()
303 if exit_msg == "checkpoint":
304 print "Dropping checkpoint at tick %d" % m5.curTick()
305 cpt_dir = os.path.join(checkpoint_dir, "cpt.%d" % m5.curTick())
306 m5.checkpoint(cpt_dir)
307 print "Checkpoint done."
308 else:
309 print exit_msg, " @ ", m5.curTick()
310 break
311
312 sys.exit(event.getCode())
313
314
315def main():
316 parser = argparse.ArgumentParser(
317 description="Generic ARM big.LITTLE configuration")
318 addOptions(parser)
319 options = parser.parse_args()
320 root = build(options)
321 instantiate(options)
322 run()
323
324
325if __name__ == "__m5_main__":
326 main()
| 119
120 sys.mem_ctrls = SimpleMemory(range=sys._mem_range)
121 sys.mem_ctrls.port = sys.membus.master
122
123 sys.connect()
124
125 # Attach disk images
126 if disks:
127 def cow_disk(image_file):
128 image = CowDiskImage()
129 image.child.image_file = SysPaths.disk(image_file)
130 return image
131
132 sys.disk_images = [ cow_disk(f) for f in disks ]
133 sys.pci_vio_block = [ PciVirtIO(vio=VirtIOBlock(image=img))
134 for img in sys.disk_images ]
135 for dev in sys.pci_vio_block:
136 sys.attach_pci(dev)
137
138 sys.realview.setupBootLoader(sys.membus, sys, SysPaths.binary)
139
140 return sys
141
142cpu_types = {
143 "atomic" : (AtomicCluster, AtomicCluster),
144 "timing" : (BigCluster, LittleCluster),
145 "exynos" : (Ex5BigCluster, Ex5LittleCluster),
146}
147
148# Only add the KVM CPU if it has been compiled into gem5
149if devices.have_kvm:
150 cpu_types["kvm"] = (KvmCluster, KvmCluster)
151
152
153def addOptions(parser):
154 parser.add_argument("--restore-from", type=str, default=None,
155 help="Restore from checkpoint")
156 parser.add_argument("--dtb", type=str, default=default_dtb,
157 help="DTB file to load")
158 parser.add_argument("--kernel", type=str, default=default_kernel,
159 help="Linux kernel")
160 parser.add_argument("--disk", action="append", type=str, default=[],
161 help="Disks to instantiate")
162 parser.add_argument("--bootscript", type=str, default=default_rcs,
163 help="Linux bootscript")
164 parser.add_argument("--cpu-type", type=str, choices=cpu_types.keys(),
165 default="timing",
166 help="CPU simulation mode. Default: %(default)s")
167 parser.add_argument("--kernel-init", type=str, default="/sbin/init",
168 help="Override init")
169 parser.add_argument("--big-cpus", type=int, default=1,
170 help="Number of big CPUs to instantiate")
171 parser.add_argument("--little-cpus", type=int, default=1,
172 help="Number of little CPUs to instantiate")
173 parser.add_argument("--caches", action="store_true", default=False,
174 help="Instantiate caches")
175 parser.add_argument("--last-cache-level", type=int, default=2,
176 help="Last level of caches (e.g. 3 for L3)")
177 parser.add_argument("--big-cpu-clock", type=str, default="2GHz",
178 help="Big CPU clock frequency")
179 parser.add_argument("--little-cpu-clock", type=str, default="1GHz",
180 help="Little CPU clock frequency")
181 parser.add_argument("--sim-quantum", type=str, default="1ms",
182 help="Simulation quantum for parallel simulation. " \
183 "Default: %(default)s")
184 return parser
185
186def build(options):
187 m5.ticks.fixGlobalFrequency()
188
189 kernel_cmd = [
190 "earlyprintk=pl011,0x1c090000",
191 "console=ttyAMA0",
192 "lpj=19988480",
193 "norandmaps",
194 "loglevel=8",
195 "mem=%s" % default_mem_size,
196 "root=/dev/vda1",
197 "rw",
198 "init=%s" % options.kernel_init,
199 "vmalloc=768MB",
200 ]
201
202 root = Root(full_system=True)
203
204 disks = [default_disk] if len(options.disk) == 0 else options.disk
205 system = createSystem(options.caches,
206 options.kernel,
207 options.bootscript,
208 disks=disks)
209
210 root.system = system
211 system.boot_osflags = " ".join(kernel_cmd)
212
213 if options.big_cpus + options.little_cpus == 0:
214 m5.util.panic("Empty CPU clusters")
215
216 big_model, little_model = cpu_types[options.cpu_type]
217
218 all_cpus = []
219 # big cluster
220 if options.big_cpus > 0:
221 system.bigCluster = big_model(system, options.big_cpus,
222 options.big_cpu_clock)
223 system.mem_mode = system.bigCluster.memoryMode()
224 all_cpus += system.bigCluster.cpus
225
226 # little cluster
227 if options.little_cpus > 0:
228 system.littleCluster = little_model(system, options.little_cpus,
229 options.little_cpu_clock)
230 system.mem_mode = system.littleCluster.memoryMode()
231 all_cpus += system.littleCluster.cpus
232
233 # Figure out the memory mode
234 if options.big_cpus > 0 and options.little_cpus > 0 and \
235 system.littleCluster.memoryMode() != system.littleCluster.memoryMode():
236 m5.util.panic("Memory mode missmatch among CPU clusters")
237
238
239 # create caches
240 system.addCaches(options.caches, options.last_cache_level)
241 if not options.caches:
242 if options.big_cpus > 0 and system.bigCluster.requireCaches():
243 m5.util.panic("Big CPU model requires caches")
244 if options.little_cpus > 0 and system.littleCluster.requireCaches():
245 m5.util.panic("Little CPU model requires caches")
246
247 # Create a KVM VM and do KVM-specific configuration
248 if issubclass(big_model, KvmCluster):
249 _build_kvm(system, all_cpus)
250
251 # Linux device tree
252 system.dtb_filename = SysPaths.binary(options.dtb)
253
254 return root
255
256def _build_kvm(system, cpus):
257 system.kvm_vm = KvmVM()
258
259 # Assign KVM CPUs to their own event queues / threads. This
260 # has to be done after creating caches and other child objects
261 # since these mustn't inherit the CPU event queue.
262 if len(cpus) > 1:
263 device_eq = 0
264 first_cpu_eq = 1
265 for idx, cpu in enumerate(cpus):
266 # Child objects usually inherit the parent's event
267 # queue. Override that and use the same event queue for
268 # all devices.
269 for obj in cpu.descendants():
270 obj.eventq_index = device_eq
271 cpu.eventq_index = first_cpu_eq + idx
272
273
274
275def instantiate(options, checkpoint_dir=None):
276 # Setup the simulation quantum if we are running in PDES-mode
277 # (e.g., when using KVM)
278 root = Root.getInstance()
279 if root and _using_pdes(root):
280 m5.util.inform("Running in PDES mode with a %s simulation quantum.",
281 options.sim_quantum)
282 root.sim_quantum = _to_ticks(options.sim_quantum)
283
284 # Get and load from the chkpt or simpoint checkpoint
285 if options.restore_from:
286 if checkpoint_dir and not os.path.isabs(options.restore_from):
287 cpt = os.path.join(checkpoint_dir, options.restore_from)
288 else:
289 cpt = options.restore_from
290
291 m5.util.inform("Restoring from checkpoint %s", cpt)
292 m5.instantiate(cpt)
293 else:
294 m5.instantiate()
295
296
297def run(checkpoint_dir=m5.options.outdir):
298 # start simulation (and drop checkpoints when requested)
299 while True:
300 event = m5.simulate()
301 exit_msg = event.getCause()
302 if exit_msg == "checkpoint":
303 print "Dropping checkpoint at tick %d" % m5.curTick()
304 cpt_dir = os.path.join(checkpoint_dir, "cpt.%d" % m5.curTick())
305 m5.checkpoint(cpt_dir)
306 print "Checkpoint done."
307 else:
308 print exit_msg, " @ ", m5.curTick()
309 break
310
311 sys.exit(event.getCode())
312
313
314def main():
315 parser = argparse.ArgumentParser(
316 description="Generic ARM big.LITTLE configuration")
317 addOptions(parser)
318 options = parser.parse_args()
319 root = build(options)
320 instantiate(options)
321 run()
322
323
324if __name__ == "__m5_main__":
325 main()
|