1# Copyright (c) 2016 ARM Limited
2# All rights reserved.
3#
4# The license below extends only to copyright in the software and shall
5# not be construed as granting a license to any other intellectual
6# property including but not limited to intellectual property relating
7# to a hardware implementation of the functionality of the software
8# licensed hereunder. You may use the software subject to the license
9# terms below provided that you ensure that this notice is replicated

--- 194 unchanged lines hidden (view full) ---

204 m5.util.panic("Little CPU model requires caches")
205
206 # Linux device tree
207 system.dtb_filename = SysPaths.binary(options.dtb)
208
209 return root
210
211
212def instantiate(checkpoint_path=None):
213 # Get and load from the chkpt or simpoint checkpoint
214 if checkpoint_path is not None:
215 m5.util.inform("Restoring from checkpoint %s", checkpoint_path)
216 m5.instantiate(checkpoint_path)
217 else:
218 m5.instantiate()
219
220
221def run(checkpoint_dir=m5.options.outdir):
222 # start simulation (and drop checkpoints when requested)
223 while True:
224 event = m5.simulate()

--- 11 unchanged lines hidden (view full) ---

236
237
238def main():
239 parser = argparse.ArgumentParser(
240 description="Generic ARM big.LITTLE configuration")
241 addOptions(parser)
242 options = parser.parse_args()
243 root = build(options)
244 instantiate(options.restore_from)
245 run()
246
247
248if __name__ == "__m5_main__":
249 main()