| devices.py (13635:d9dcebb1d6b6) | devices.py (13636:3b55e4bae1d8) |
|---|---|
| 1# Copyright (c) 2016-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 193 unchanged lines hidden (view full) --- 202 self.terminal = Terminal() 203 self.vncserver = VncServer() 204 205 self.iobus = IOXBar() 206 # CPUs->PIO 207 self.iobridge = Bridge(delay='50ns') 208 # Device DMA -> MEM 209 mem_range = self.realview._mem_regions[0] | 1# Copyright (c) 2016-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 193 unchanged lines hidden (view full) --- 202 self.terminal = Terminal() 203 self.vncserver = VncServer() 204 205 self.iobus = IOXBar() 206 # CPUs->PIO 207 self.iobridge = Bridge(delay='50ns') 208 # Device DMA -> MEM 209 mem_range = self.realview._mem_regions[0] |
| 210 max_size = long(mem_range[1]) 211 assert max_size >= long(Addr(mem_size)) 212 self.mem_ranges = [ AddrRange(start=mem_range[0], size=mem_size) ] | 210 assert long(mem_range.size()) >= long(Addr(mem_size)) 211 self.mem_ranges = [ AddrRange(start=mem_range.start, size=mem_size) ] |
| 213 self._caches = caches 214 if self._caches: 215 self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]]) 216 else: 217 self.dmabridge = Bridge(delay='50ns', 218 ranges=[self.mem_ranges[0]]) 219 220 self._pci_devices = 0 --- 62 unchanged lines hidden --- | 212 self._caches = caches 213 if self._caches: 214 self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]]) 215 else: 216 self.dmabridge = Bridge(delay='50ns', 217 ranges=[self.mem_ranges[0]]) 218 219 self._pci_devices = 0 --- 62 unchanged lines hidden --- |