| devices.py (11936:8ab45fd19f40) | devices.py (12148:6d367c7fdb1d) |
|---|---|
| 1# Copyright (c) 2016-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 195 unchanged lines hidden (view full) --- 204 205 self.iobus = IOXBar() 206 # CPUs->PIO 207 self.iobridge = Bridge(delay='50ns') 208 # Device DMA -> MEM 209 mem_range = self.realview._mem_regions[0] 210 mem_range_size = long(mem_range[1]) - long(mem_range[0]) 211 assert mem_range_size >= long(Addr(mem_size)) | 1# Copyright (c) 2016-2017 ARM Limited 2# All rights reserved. 3# 4# The license below extends only to copyright in the software and shall 5# not be construed as granting a license to any other intellectual 6# property including but not limited to intellectual property relating 7# to a hardware implementation of the functionality of the software 8# licensed hereunder. You may use the software subject to the license --- 195 unchanged lines hidden (view full) --- 204 205 self.iobus = IOXBar() 206 # CPUs->PIO 207 self.iobridge = Bridge(delay='50ns') 208 # Device DMA -> MEM 209 mem_range = self.realview._mem_regions[0] 210 mem_range_size = long(mem_range[1]) - long(mem_range[0]) 211 assert mem_range_size >= long(Addr(mem_size)) |
| 212 self._mem_range = AddrRange(start=mem_range[0], size=mem_size) | 212 self.mem_ranges = [ AddrRange(start=mem_range[0], size=mem_size) ] |
| 213 self._caches = caches 214 if self._caches: | 213 self._caches = caches 214 if self._caches: |
| 215 self.iocache = IOCache(addr_ranges=[self._mem_range]) | 215 self.iocache = IOCache(addr_ranges=[self.mem_ranges[0]]) |
| 216 else: 217 self.dmabridge = Bridge(delay='50ns', | 216 else: 217 self.dmabridge = Bridge(delay='50ns', |
| 218 ranges=[self._mem_range]) | 218 ranges=[self.mem_ranges[0]]) |
| 219 220 self._pci_devices = 0 221 self._clusters = [] 222 self._num_cpus = 0 223 224 def attach_pci(self, dev): 225 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0) 226 self._pci_devices += 1 --- 56 unchanged lines hidden --- | 219 220 self._pci_devices = 0 221 self._clusters = [] 222 self._num_cpus = 0 223 224 def attach_pci(self, dev): 225 dev.pci_bus, dev.pci_dev, dev.pci_func = (0, self._pci_devices + 1, 0) 226 self._pci_devices += 1 --- 56 unchanged lines hidden --- |